577 lines
15 KiB
C
577 lines
15 KiB
C
/**************************************************************************
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Copyright (c) 2007-2009, Chelsio Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Neither the name of the Chelsio Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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$FreeBSD$
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***************************************************************************/
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#ifndef _CXGB_ADAPTER_H_
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#define _CXGB_ADAPTER_H_
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/condvar.h>
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#include <sys/buf_ring.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <net/if_dl.h>
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#include <netinet/in.h>
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#include <netinet/tcp_lro.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus_dma.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <cxgb_osdep.h>
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#include <sys/mbufq.h>
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struct adapter;
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struct sge_qset;
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extern int cxgb_debug;
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#ifdef DEBUG_LOCKING
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#define MTX_INIT(lock, lockname, class, flags) \
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do { \
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printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \
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mtx_init((lock), lockname, class, flags); \
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} while (0)
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#define MTX_DESTROY(lock) \
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do { \
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printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \
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mtx_destroy((lock)); \
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} while (0)
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#else
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#define MTX_INIT mtx_init
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#define MTX_DESTROY mtx_destroy
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#endif
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enum {
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LF_NO = 0,
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LF_MAYBE,
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LF_YES
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};
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struct port_info {
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struct adapter *adapter;
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struct ifnet *ifp;
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int if_flags;
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int flags;
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const struct port_type_info *port_type;
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struct cphy phy;
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struct cmac mac;
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struct link_config link_config;
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struct ifmedia media;
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struct mtx lock;
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uint32_t port_id;
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uint32_t tx_chan;
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uint32_t txpkt_intf;
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uint32_t first_qset;
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uint32_t nqsets;
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int link_fault;
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uint8_t hw_addr[ETHER_ADDR_LEN];
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struct callout link_check_ch;
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struct task link_check_task;
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struct task timer_reclaim_task;
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struct cdev *port_cdev;
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#define PORT_LOCK_NAME_LEN 32
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#define PORT_NAME_LEN 32
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char lockbuf[PORT_LOCK_NAME_LEN];
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char namebuf[PORT_NAME_LEN];
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} __aligned(L1_CACHE_BYTES);
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enum {
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/* adapter flags */
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FULL_INIT_DONE = (1 << 0),
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USING_MSI = (1 << 1),
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USING_MSIX = (1 << 2),
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QUEUES_BOUND = (1 << 3),
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FW_UPTODATE = (1 << 4),
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TPS_UPTODATE = (1 << 5),
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CXGB_SHUTDOWN = (1 << 6),
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CXGB_OFLD_INIT = (1 << 7),
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TP_PARITY_INIT = (1 << 8),
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CXGB_BUSY = (1 << 9),
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TOM_INIT_DONE = (1 << 10),
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/* port flags */
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DOOMED = (1 << 0),
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};
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#define IS_DOOMED(p) (p->flags & DOOMED)
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#define SET_DOOMED(p) do {p->flags |= DOOMED;} while (0)
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#define IS_BUSY(sc) (sc->flags & CXGB_BUSY)
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#define SET_BUSY(sc) do {sc->flags |= CXGB_BUSY;} while (0)
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#define CLR_BUSY(sc) do {sc->flags &= ~CXGB_BUSY;} while (0)
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#define FL_Q_SIZE 4096
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#define JUMBO_Q_SIZE 1024
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#define RSPQ_Q_SIZE 2048
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#define TX_ETH_Q_SIZE 1024
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#define TX_OFLD_Q_SIZE 1024
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#define TX_CTRL_Q_SIZE 256
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enum { TXQ_ETH = 0,
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TXQ_OFLD = 1,
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TXQ_CTRL = 2, };
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/*
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* work request size in bytes
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*/
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#define WR_LEN (WR_FLITS * 8)
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#define PIO_LEN (WR_LEN - sizeof(struct cpl_tx_pkt_lso))
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struct lro_state {
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unsigned short enabled;
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struct lro_ctrl ctrl;
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};
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#define RX_BUNDLE_SIZE 8
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struct rsp_desc;
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struct sge_rspq {
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uint32_t credits;
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uint32_t size;
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uint32_t cidx;
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uint32_t gen;
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uint32_t polling;
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uint32_t holdoff_tmr;
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uint32_t next_holdoff;
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uint32_t imm_data;
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uint32_t async_notif;
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uint32_t cntxt_id;
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uint32_t offload_pkts;
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uint32_t pure_rsps;
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uint32_t unhandled_irqs;
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uint32_t starved;
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bus_addr_t phys_addr;
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bus_dma_tag_t desc_tag;
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bus_dmamap_t desc_map;
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struct t3_mbuf_hdr rspq_mh;
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struct rsp_desc *desc;
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struct mtx lock;
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#define RSPQ_NAME_LEN 32
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char lockbuf[RSPQ_NAME_LEN];
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uint32_t rspq_dump_start;
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uint32_t rspq_dump_count;
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};
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struct rx_desc;
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struct rx_sw_desc;
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struct sge_fl {
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uint32_t buf_size;
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uint32_t credits;
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uint32_t size;
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uint32_t cidx;
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uint32_t pidx;
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uint32_t gen;
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uint32_t db_pending;
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bus_addr_t phys_addr;
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uint32_t cntxt_id;
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uint32_t empty;
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bus_dma_tag_t desc_tag;
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bus_dmamap_t desc_map;
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bus_dma_tag_t entry_tag;
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uma_zone_t zone;
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struct rx_desc *desc;
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struct rx_sw_desc *sdesc;
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int type;
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};
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struct tx_desc;
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struct tx_sw_desc;
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#define TXQ_TRANSMITTING 0x1
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struct sge_txq {
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uint64_t flags;
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uint32_t in_use;
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uint32_t size;
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uint32_t processed;
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uint32_t cleaned;
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uint32_t stop_thres;
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uint32_t cidx;
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uint32_t pidx;
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uint32_t gen;
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uint32_t unacked;
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uint32_t db_pending;
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struct tx_desc *desc;
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struct tx_sw_desc *sdesc;
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uint32_t token;
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bus_addr_t phys_addr;
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struct task qresume_task;
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struct task qreclaim_task;
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uint32_t cntxt_id;
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uint64_t stops;
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uint64_t restarts;
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bus_dma_tag_t desc_tag;
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bus_dmamap_t desc_map;
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bus_dma_tag_t entry_tag;
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struct mbuf_head sendq;
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struct buf_ring *txq_mr;
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struct ifaltq *txq_ifq;
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struct callout txq_timer;
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struct callout txq_watchdog;
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uint64_t txq_coalesced;
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uint32_t txq_skipped;
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uint32_t txq_enqueued;
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uint32_t txq_dump_start;
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uint32_t txq_dump_count;
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uint64_t txq_direct_packets;
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uint64_t txq_direct_bytes;
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uint64_t txq_frees;
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struct sg_ent txq_sgl[TX_MAX_SEGS / 2 + 1];
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};
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#define SGE_PSTAT_MAX (SGE_PSTAT_VLANINS+1)
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#define QS_EXITING 0x1
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#define QS_RUNNING 0x2
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#define QS_BOUND 0x4
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#define QS_FLUSHING 0x8
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#define QS_TIMEOUT 0x10
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struct sge_qset {
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struct sge_rspq rspq;
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struct sge_fl fl[SGE_RXQ_PER_SET];
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struct lro_state lro;
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struct sge_txq txq[SGE_TXQ_PER_SET];
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uint32_t txq_stopped; /* which Tx queues are stopped */
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struct port_info *port;
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struct adapter *adap;
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int idx; /* qset # */
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int qs_flags;
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int coalescing;
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struct cv qs_cv;
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struct mtx lock;
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#define QS_NAME_LEN 32
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char namebuf[QS_NAME_LEN];
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};
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struct sge {
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struct sge_qset qs[SGE_QSETS];
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struct mtx reg_lock;
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};
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struct filter_info;
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typedef int (*cpl_handler_t)(struct sge_qset *, struct rsp_desc *,
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struct mbuf *);
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struct adapter {
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SLIST_ENTRY(adapter) link;
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device_t dev;
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int flags;
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/* PCI register resources */
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int regs_rid;
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struct resource *regs_res;
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int udbs_rid;
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struct resource *udbs_res;
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bus_space_handle_t bh;
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bus_space_tag_t bt;
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bus_size_t mmio_len;
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uint32_t link_width;
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/* DMA resources */
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bus_dma_tag_t parent_dmat;
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bus_dma_tag_t rx_dmat;
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bus_dma_tag_t rx_jumbo_dmat;
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bus_dma_tag_t tx_dmat;
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/* Interrupt resources */
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struct resource *irq_res;
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int irq_rid;
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void *intr_tag;
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uint32_t msix_regs_rid;
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struct resource *msix_regs_res;
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struct resource *msix_irq_res[SGE_QSETS];
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int msix_irq_rid[SGE_QSETS];
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void *msix_intr_tag[SGE_QSETS];
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uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */
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uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */
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uint16_t rspq_map[RSS_TABLE_SIZE]; /* maps 7-bit cookie to qidx */
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union {
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uint8_t fill[SGE_QSETS];
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uint64_t coalesce;
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} u;
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#define tunq_fill u.fill
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#define tunq_coalesce u.coalesce
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struct filter_info *filters;
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/* Tasks */
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struct task slow_intr_task;
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struct task tick_task;
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struct taskqueue *tq;
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struct callout cxgb_tick_ch;
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struct callout sge_timer_ch;
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/* Register lock for use by the hardware layer */
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struct mtx mdio_lock;
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struct mtx elmer_lock;
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/* Bookkeeping for the hardware layer */
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struct adapter_params params;
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unsigned int slow_intr_mask;
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unsigned long irq_stats[IRQ_NUM_STATS];
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struct sge sge;
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struct mc7 pmrx;
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struct mc7 pmtx;
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struct mc7 cm;
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struct mc5 mc5;
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struct port_info port[MAX_NPORTS];
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device_t portdev[MAX_NPORTS];
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#ifdef TCP_OFFLOAD
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void *tom_softc;
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void *iwarp_softc;
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#endif
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char fw_version[64];
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char port_types[MAX_NPORTS + 1];
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uint32_t open_device_map;
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#ifdef TCP_OFFLOAD
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int offload_map;
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#endif
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struct mtx lock;
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driver_intr_t *cxgb_intr;
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int msi_count;
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#define ADAPTER_LOCK_NAME_LEN 32
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char lockbuf[ADAPTER_LOCK_NAME_LEN];
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char reglockbuf[ADAPTER_LOCK_NAME_LEN];
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char mdiolockbuf[ADAPTER_LOCK_NAME_LEN];
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char elmerlockbuf[ADAPTER_LOCK_NAME_LEN];
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int timestamp;
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#ifdef TCP_OFFLOAD
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#define NUM_CPL_HANDLERS 0xa7
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cpl_handler_t cpl_handler[NUM_CPL_HANDLERS] __aligned(CACHE_LINE_SIZE);
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#endif
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};
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struct t3_rx_mode {
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uint32_t idx;
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struct port_info *port;
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};
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#define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock)
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#define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock)
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#define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock)
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#define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock)
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#define PORT_LOCK(port) mtx_lock(&(port)->lock);
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#define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
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#define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF)
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#define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock)
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#define PORT_LOCK_ASSERT_NOTOWNED(port) mtx_assert(&(port)->lock, MA_NOTOWNED)
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#define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED)
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#define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock);
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#define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock);
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#define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF)
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#define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock)
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#define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MA_NOTOWNED)
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#define ADAPTER_LOCK_ASSERT_OWNED(adap) mtx_assert(&(adap)->lock, MA_OWNED)
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static __inline uint32_t
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t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
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{
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return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));
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}
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static __inline void
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t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
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{
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bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);
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}
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static __inline void
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t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)
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{
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*val = pci_read_config(adapter->dev, reg, 4);
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}
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static __inline void
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t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)
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{
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pci_write_config(adapter->dev, reg, val, 4);
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}
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static __inline void
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t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)
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{
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*val = pci_read_config(adapter->dev, reg, 2);
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}
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static __inline void
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t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)
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{
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pci_write_config(adapter->dev, reg, val, 2);
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}
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static __inline uint8_t *
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t3_get_next_mcaddr(struct t3_rx_mode *rm)
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{
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uint8_t *macaddr = NULL;
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struct ifnet *ifp = rm->port->ifp;
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struct ifmultiaddr *ifma;
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int i = 0;
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if_maddr_rlock(ifp);
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TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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continue;
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if (i == rm->idx) {
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macaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
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break;
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}
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i++;
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}
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if_maddr_runlock(ifp);
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rm->idx++;
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return (macaddr);
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}
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static __inline void
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t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port)
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{
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rm->idx = 0;
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rm->port = port;
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}
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static __inline struct port_info *
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adap2pinfo(struct adapter *adap, int idx)
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{
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return &adap->port[idx];
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}
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int t3_os_find_pci_capability(adapter_t *adapter, int cap);
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int t3_os_pci_save_state(struct adapter *adapter);
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int t3_os_pci_restore_state(struct adapter *adapter);
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void t3_os_link_intr(struct port_info *);
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void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
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int speed, int duplex, int fc, int mac_was_reset);
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void t3_os_phymod_changed(struct adapter *adap, int port_id);
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void t3_sge_err_intr_handler(adapter_t *adapter);
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#ifdef TCP_OFFLOAD
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int t3_offload_tx(struct adapter *, struct mbuf *);
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#endif
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void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]);
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int t3_mgmt_tx(adapter_t *adap, struct mbuf *m);
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int t3_register_cpl_handler(struct adapter *, int, cpl_handler_t);
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int t3_sge_alloc(struct adapter *);
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int t3_sge_free(struct adapter *);
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int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *,
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int, struct port_info *);
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void t3_free_sge_resources(adapter_t *, int);
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void t3_sge_start(adapter_t *);
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void t3_sge_stop(adapter_t *);
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void t3b_intr(void *data);
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void t3_intr_msi(void *data);
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void t3_intr_msix(void *data);
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int t3_sge_init_adapter(adapter_t *);
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int t3_sge_reset_adapter(adapter_t *);
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int t3_sge_init_port(struct port_info *);
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void t3_free_tx_desc(struct sge_qset *qs, int n, int qid);
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void t3_rx_eth(struct adapter *adap, struct mbuf *m, int ethpad);
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void t3_add_attach_sysctls(adapter_t *sc);
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void t3_add_configured_sysctls(adapter_t *sc);
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int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
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unsigned char *data);
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void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
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/*
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* XXX figure out how we can return this to being private to sge
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*/
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#define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC))
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#define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field)))
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static __inline struct sge_qset *
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fl_to_qset(struct sge_fl *q, int qidx)
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{
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return container_of(q, struct sge_qset, fl[qidx]);
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}
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static __inline struct sge_qset *
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rspq_to_qset(struct sge_rspq *q)
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{
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return container_of(q, struct sge_qset, rspq);
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}
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static __inline struct sge_qset *
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txq_to_qset(struct sge_txq *q, int qidx)
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{
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return container_of(q, struct sge_qset, txq[qidx]);
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}
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#undef container_of
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#define OFFLOAD_DEVMAP_BIT (1 << MAX_NPORTS)
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static inline int offload_running(adapter_t *adapter)
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{
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return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
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}
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void cxgb_tx_watchdog(void *arg);
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int cxgb_transmit(struct ifnet *ifp, struct mbuf *m);
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void cxgb_qflush(struct ifnet *ifp);
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void t3_iterate(void (*)(struct adapter *, void *), void *);
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#endif
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