795 lines
15 KiB
NASM
795 lines
15 KiB
NASM
/* Copyright (C) 2000, 2001, 2003, 2005 Free Software Foundation, Inc.
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Contributed by James E. Wilson <wilson@cygnus.com>.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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/* As a special exception, if you link this library with other files,
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some of which are compiled with GCC, to produce an executable,
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this library does not by itself cause the resulting executable
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to be covered by the GNU General Public License.
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This exception does not however invalidate any other reasons why
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the executable file might be covered by the GNU General Public License. */
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#ifdef L__divxf3
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// Compute a 80-bit IEEE double-extended quotient.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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// alternative.
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//
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// farg0 holds the dividend. farg1 holds the divisor.
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//
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// __divtf3 is an alternate symbol name for backward compatibility.
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.text
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.align 16
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.global __divxf3
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.global __divtf3
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.proc __divxf3
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__divxf3:
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__divtf3:
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cmp.eq p7, p0 = r0, r0
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frcpa.s0 f10, p6 = farg0, farg1
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;;
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(p6) cmp.ne p7, p0 = r0, r0
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.pred.rel.mutex p6, p7
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(p6) fnma.s1 f11 = farg1, f10, f1
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(p6) fma.s1 f12 = farg0, f10, f0
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;;
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(p6) fma.s1 f13 = f11, f11, f0
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(p6) fma.s1 f14 = f11, f11, f11
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;;
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(p6) fma.s1 f11 = f13, f13, f11
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(p6) fma.s1 f13 = f14, f10, f10
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;;
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(p6) fma.s1 f10 = f13, f11, f10
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(p6) fnma.s1 f11 = farg1, f12, farg0
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;;
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(p6) fma.s1 f11 = f11, f10, f12
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(p6) fnma.s1 f12 = farg1, f10, f1
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;;
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(p6) fma.s1 f10 = f12, f10, f10
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(p6) fnma.s1 f12 = farg1, f11, farg0
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;;
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(p6) fma.s0 fret0 = f12, f10, f11
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(p7) mov fret0 = f10
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br.ret.sptk rp
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.endp __divxf3
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#endif
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#ifdef L__divdf3
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// Compute a 64-bit IEEE double quotient.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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// alternative.
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//
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// farg0 holds the dividend. farg1 holds the divisor.
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.text
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.align 16
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.global __divdf3
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.proc __divdf3
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__divdf3:
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cmp.eq p7, p0 = r0, r0
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frcpa.s0 f10, p6 = farg0, farg1
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;;
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(p6) cmp.ne p7, p0 = r0, r0
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.pred.rel.mutex p6, p7
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(p6) fmpy.s1 f11 = farg0, f10
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(p6) fnma.s1 f12 = farg1, f10, f1
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;;
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(p6) fma.s1 f11 = f12, f11, f11
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(p6) fmpy.s1 f13 = f12, f12
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;;
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(p6) fma.s1 f10 = f12, f10, f10
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(p6) fma.s1 f11 = f13, f11, f11
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;;
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(p6) fmpy.s1 f12 = f13, f13
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(p6) fma.s1 f10 = f13, f10, f10
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;;
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(p6) fma.d.s1 f11 = f12, f11, f11
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(p6) fma.s1 f10 = f12, f10, f10
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;;
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(p6) fnma.d.s1 f8 = farg1, f11, farg0
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;;
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(p6) fma.d fret0 = f8, f10, f11
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(p7) mov fret0 = f10
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br.ret.sptk rp
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;;
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.endp __divdf3
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#endif
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#ifdef L__divsf3
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// Compute a 32-bit IEEE float quotient.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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// alternative.
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//
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// farg0 holds the dividend. farg1 holds the divisor.
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.text
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.align 16
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.global __divsf3
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.proc __divsf3
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__divsf3:
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cmp.eq p7, p0 = r0, r0
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frcpa.s0 f10, p6 = farg0, farg1
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;;
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(p6) cmp.ne p7, p0 = r0, r0
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.pred.rel.mutex p6, p7
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(p6) fmpy.s1 f8 = farg0, f10
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(p6) fnma.s1 f9 = farg1, f10, f1
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;;
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(p6) fma.s1 f8 = f9, f8, f8
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(p6) fmpy.s1 f9 = f9, f9
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;;
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(p6) fma.s1 f8 = f9, f8, f8
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(p6) fmpy.s1 f9 = f9, f9
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;;
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(p6) fma.d.s1 f10 = f9, f8, f8
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;;
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(p6) fnorm.s.s0 fret0 = f10
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(p7) mov fret0 = f10
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br.ret.sptk rp
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;;
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.endp __divsf3
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#endif
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#ifdef L__divdi3
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// Compute a 64-bit integer quotient.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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// alternative.
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//
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// in0 holds the dividend. in1 holds the divisor.
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.text
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.align 16
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.global __divdi3
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.proc __divdi3
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__divdi3:
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.regstk 2,0,0,0
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// Transfer inputs to FP registers.
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setf.sig f8 = in0
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setf.sig f9 = in1
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// Check divide by zero.
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cmp.ne.unc p0,p7=0,in1
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;;
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// Convert the inputs to FP, so that they won't be treated as unsigned.
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fcvt.xf f8 = f8
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fcvt.xf f9 = f9
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(p7) break 1
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;;
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// Compute the reciprocal approximation.
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frcpa.s1 f10, p6 = f8, f9
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;;
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// 3 Newton-Raphson iterations.
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(p6) fnma.s1 f11 = f9, f10, f1
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(p6) fmpy.s1 f12 = f8, f10
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;;
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(p6) fmpy.s1 f13 = f11, f11
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(p6) fma.s1 f12 = f11, f12, f12
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;;
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(p6) fma.s1 f10 = f11, f10, f10
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(p6) fma.s1 f11 = f13, f12, f12
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;;
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(p6) fma.s1 f10 = f13, f10, f10
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(p6) fnma.s1 f12 = f9, f11, f8
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;;
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(p6) fma.s1 f10 = f12, f10, f11
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;;
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// Round quotient to an integer.
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fcvt.fx.trunc.s1 f10 = f10
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;;
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// Transfer result to GP registers.
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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.endp __divdi3
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#endif
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#ifdef L__moddi3
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// Compute a 64-bit integer modulus.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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// alternative.
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//
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// in0 holds the dividend (a). in1 holds the divisor (b).
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.text
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.align 16
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.global __moddi3
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.proc __moddi3
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__moddi3:
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.regstk 2,0,0,0
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// Transfer inputs to FP registers.
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setf.sig f14 = in0
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setf.sig f9 = in1
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// Check divide by zero.
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cmp.ne.unc p0,p7=0,in1
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;;
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// Convert the inputs to FP, so that they won't be treated as unsigned.
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fcvt.xf f8 = f14
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fcvt.xf f9 = f9
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(p7) break 1
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;;
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// Compute the reciprocal approximation.
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frcpa.s1 f10, p6 = f8, f9
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;;
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// 3 Newton-Raphson iterations.
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(p6) fmpy.s1 f12 = f8, f10
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(p6) fnma.s1 f11 = f9, f10, f1
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;;
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(p6) fma.s1 f12 = f11, f12, f12
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(p6) fmpy.s1 f13 = f11, f11
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;;
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(p6) fma.s1 f10 = f11, f10, f10
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(p6) fma.s1 f11 = f13, f12, f12
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;;
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sub in1 = r0, in1
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(p6) fma.s1 f10 = f13, f10, f10
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(p6) fnma.s1 f12 = f9, f11, f8
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;;
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setf.sig f9 = in1
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(p6) fma.s1 f10 = f12, f10, f11
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;;
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fcvt.fx.trunc.s1 f10 = f10
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;;
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// r = q * (-b) + a
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xma.l f10 = f10, f9, f14
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;;
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// Transfer result to GP registers.
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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.endp __moddi3
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#endif
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#ifdef L__udivdi3
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// Compute a 64-bit unsigned integer quotient.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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// alternative.
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//
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// in0 holds the dividend. in1 holds the divisor.
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.text
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.align 16
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.global __udivdi3
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.proc __udivdi3
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__udivdi3:
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.regstk 2,0,0,0
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// Transfer inputs to FP registers.
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setf.sig f8 = in0
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setf.sig f9 = in1
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// Check divide by zero.
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cmp.ne.unc p0,p7=0,in1
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;;
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// Convert the inputs to FP, to avoid FP software-assist faults.
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fcvt.xuf.s1 f8 = f8
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fcvt.xuf.s1 f9 = f9
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(p7) break 1
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;;
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// Compute the reciprocal approximation.
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frcpa.s1 f10, p6 = f8, f9
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;;
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// 3 Newton-Raphson iterations.
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(p6) fnma.s1 f11 = f9, f10, f1
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(p6) fmpy.s1 f12 = f8, f10
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;;
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(p6) fmpy.s1 f13 = f11, f11
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(p6) fma.s1 f12 = f11, f12, f12
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;;
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(p6) fma.s1 f10 = f11, f10, f10
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(p6) fma.s1 f11 = f13, f12, f12
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;;
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(p6) fma.s1 f10 = f13, f10, f10
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(p6) fnma.s1 f12 = f9, f11, f8
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;;
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(p6) fma.s1 f10 = f12, f10, f11
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;;
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// Round quotient to an unsigned integer.
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fcvt.fxu.trunc.s1 f10 = f10
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;;
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// Transfer result to GP registers.
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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.endp __udivdi3
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#endif
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#ifdef L__umoddi3
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// Compute a 64-bit unsigned integer modulus.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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// alternative.
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//
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// in0 holds the dividend (a). in1 holds the divisor (b).
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.text
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.align 16
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.global __umoddi3
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.proc __umoddi3
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__umoddi3:
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.regstk 2,0,0,0
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// Transfer inputs to FP registers.
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setf.sig f14 = in0
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setf.sig f9 = in1
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// Check divide by zero.
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cmp.ne.unc p0,p7=0,in1
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;;
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// Convert the inputs to FP, to avoid FP software assist faults.
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fcvt.xuf.s1 f8 = f14
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fcvt.xuf.s1 f9 = f9
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(p7) break 1;
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;;
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// Compute the reciprocal approximation.
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frcpa.s1 f10, p6 = f8, f9
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;;
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// 3 Newton-Raphson iterations.
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(p6) fmpy.s1 f12 = f8, f10
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(p6) fnma.s1 f11 = f9, f10, f1
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;;
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(p6) fma.s1 f12 = f11, f12, f12
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(p6) fmpy.s1 f13 = f11, f11
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;;
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(p6) fma.s1 f10 = f11, f10, f10
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(p6) fma.s1 f11 = f13, f12, f12
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;;
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sub in1 = r0, in1
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(p6) fma.s1 f10 = f13, f10, f10
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(p6) fnma.s1 f12 = f9, f11, f8
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;;
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setf.sig f9 = in1
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(p6) fma.s1 f10 = f12, f10, f11
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;;
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// Round quotient to an unsigned integer.
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fcvt.fxu.trunc.s1 f10 = f10
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;;
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// r = q * (-b) + a
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xma.l f10 = f10, f9, f14
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;;
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// Transfer result to GP registers.
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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.endp __umoddi3
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#endif
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#ifdef L__divsi3
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// Compute a 32-bit integer quotient.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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// alternative.
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//
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// in0 holds the dividend. in1 holds the divisor.
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.text
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.align 16
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.global __divsi3
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.proc __divsi3
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__divsi3:
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.regstk 2,0,0,0
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// Check divide by zero.
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cmp.ne.unc p0,p7=0,in1
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sxt4 in0 = in0
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sxt4 in1 = in1
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;;
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setf.sig f8 = in0
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setf.sig f9 = in1
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(p7) break 1
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;;
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mov r2 = 0x0ffdd
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fcvt.xf f8 = f8
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fcvt.xf f9 = f9
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;;
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setf.exp f11 = r2
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frcpa.s1 f10, p6 = f8, f9
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;;
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(p6) fmpy.s1 f8 = f8, f10
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(p6) fnma.s1 f9 = f9, f10, f1
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;;
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(p6) fma.s1 f8 = f9, f8, f8
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(p6) fma.s1 f9 = f9, f9, f11
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;;
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(p6) fma.s1 f10 = f9, f8, f8
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;;
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fcvt.fx.trunc.s1 f10 = f10
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;;
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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.endp __divsi3
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#endif
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#ifdef L__modsi3
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// Compute a 32-bit integer modulus.
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//
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// From the Intel IA-64 Optimization Guide, choose the minimum latency
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|
// alternative.
|
|
//
|
|
// in0 holds the dividend. in1 holds the divisor.
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.text
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.align 16
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.global __modsi3
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.proc __modsi3
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__modsi3:
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.regstk 2,0,0,0
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mov r2 = 0x0ffdd
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sxt4 in0 = in0
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sxt4 in1 = in1
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;;
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setf.sig f13 = r32
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setf.sig f9 = r33
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// Check divide by zero.
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cmp.ne.unc p0,p7=0,in1
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;;
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sub in1 = r0, in1
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fcvt.xf f8 = f13
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fcvt.xf f9 = f9
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;;
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setf.exp f11 = r2
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frcpa.s1 f10, p6 = f8, f9
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(p7) break 1
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;;
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(p6) fmpy.s1 f12 = f8, f10
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(p6) fnma.s1 f10 = f9, f10, f1
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;;
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setf.sig f9 = in1
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(p6) fma.s1 f12 = f10, f12, f12
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(p6) fma.s1 f10 = f10, f10, f11
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;;
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(p6) fma.s1 f10 = f10, f12, f12
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;;
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fcvt.fx.trunc.s1 f10 = f10
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;;
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xma.l f10 = f10, f9, f13
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;;
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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.endp __modsi3
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#endif
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|
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#ifdef L__udivsi3
|
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// Compute a 32-bit unsigned integer quotient.
|
|
//
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|
// From the Intel IA-64 Optimization Guide, choose the minimum latency
|
|
// alternative.
|
|
//
|
|
// in0 holds the dividend. in1 holds the divisor.
|
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|
|
.text
|
|
.align 16
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|
.global __udivsi3
|
|
.proc __udivsi3
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|
__udivsi3:
|
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.regstk 2,0,0,0
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mov r2 = 0x0ffdd
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zxt4 in0 = in0
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zxt4 in1 = in1
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;;
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setf.sig f8 = in0
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setf.sig f9 = in1
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// Check divide by zero.
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cmp.ne.unc p0,p7=0,in1
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;;
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fcvt.xf f8 = f8
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fcvt.xf f9 = f9
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(p7) break 1
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;;
|
|
setf.exp f11 = r2
|
|
frcpa.s1 f10, p6 = f8, f9
|
|
;;
|
|
(p6) fmpy.s1 f8 = f8, f10
|
|
(p6) fnma.s1 f9 = f9, f10, f1
|
|
;;
|
|
(p6) fma.s1 f8 = f9, f8, f8
|
|
(p6) fma.s1 f9 = f9, f9, f11
|
|
;;
|
|
(p6) fma.s1 f10 = f9, f8, f8
|
|
;;
|
|
fcvt.fxu.trunc.s1 f10 = f10
|
|
;;
|
|
getf.sig ret0 = f10
|
|
br.ret.sptk rp
|
|
;;
|
|
.endp __udivsi3
|
|
#endif
|
|
|
|
#ifdef L__umodsi3
|
|
// Compute a 32-bit unsigned integer modulus.
|
|
//
|
|
// From the Intel IA-64 Optimization Guide, choose the minimum latency
|
|
// alternative.
|
|
//
|
|
// in0 holds the dividend. in1 holds the divisor.
|
|
|
|
.text
|
|
.align 16
|
|
.global __umodsi3
|
|
.proc __umodsi3
|
|
__umodsi3:
|
|
.regstk 2,0,0,0
|
|
mov r2 = 0x0ffdd
|
|
zxt4 in0 = in0
|
|
zxt4 in1 = in1
|
|
;;
|
|
setf.sig f13 = in0
|
|
setf.sig f9 = in1
|
|
// Check divide by zero.
|
|
cmp.ne.unc p0,p7=0,in1
|
|
;;
|
|
sub in1 = r0, in1
|
|
fcvt.xf f8 = f13
|
|
fcvt.xf f9 = f9
|
|
;;
|
|
setf.exp f11 = r2
|
|
frcpa.s1 f10, p6 = f8, f9
|
|
(p7) break 1;
|
|
;;
|
|
(p6) fmpy.s1 f12 = f8, f10
|
|
(p6) fnma.s1 f10 = f9, f10, f1
|
|
;;
|
|
setf.sig f9 = in1
|
|
(p6) fma.s1 f12 = f10, f12, f12
|
|
(p6) fma.s1 f10 = f10, f10, f11
|
|
;;
|
|
(p6) fma.s1 f10 = f10, f12, f12
|
|
;;
|
|
fcvt.fxu.trunc.s1 f10 = f10
|
|
;;
|
|
xma.l f10 = f10, f9, f13
|
|
;;
|
|
getf.sig ret0 = f10
|
|
br.ret.sptk rp
|
|
;;
|
|
.endp __umodsi3
|
|
#endif
|
|
|
|
#ifdef L__save_stack_nonlocal
|
|
// Notes on save/restore stack nonlocal: We read ar.bsp but write
|
|
// ar.bspstore. This is because ar.bsp can be read at all times
|
|
// (independent of the RSE mode) but since it's read-only we need to
|
|
// restore the value via ar.bspstore. This is OK because
|
|
// ar.bsp==ar.bspstore after executing "flushrs".
|
|
|
|
// void __ia64_save_stack_nonlocal(void *save_area, void *stack_pointer)
|
|
|
|
.text
|
|
.align 16
|
|
.global __ia64_save_stack_nonlocal
|
|
.proc __ia64_save_stack_nonlocal
|
|
__ia64_save_stack_nonlocal:
|
|
{ .mmf
|
|
alloc r18 = ar.pfs, 2, 0, 0, 0
|
|
mov r19 = ar.rsc
|
|
;;
|
|
}
|
|
{ .mmi
|
|
flushrs
|
|
st8 [in0] = in1, 24
|
|
and r19 = 0x1c, r19
|
|
;;
|
|
}
|
|
{ .mmi
|
|
st8 [in0] = r18, -16
|
|
mov ar.rsc = r19
|
|
or r19 = 0x3, r19
|
|
;;
|
|
}
|
|
{ .mmi
|
|
mov r16 = ar.bsp
|
|
mov r17 = ar.rnat
|
|
adds r2 = 8, in0
|
|
;;
|
|
}
|
|
{ .mmi
|
|
st8 [in0] = r16
|
|
st8 [r2] = r17
|
|
}
|
|
{ .mib
|
|
mov ar.rsc = r19
|
|
br.ret.sptk.few rp
|
|
;;
|
|
}
|
|
.endp __ia64_save_stack_nonlocal
|
|
#endif
|
|
|
|
#ifdef L__nonlocal_goto
|
|
// void __ia64_nonlocal_goto(void *target_label, void *save_area,
|
|
// void *static_chain);
|
|
|
|
.text
|
|
.align 16
|
|
.global __ia64_nonlocal_goto
|
|
.proc __ia64_nonlocal_goto
|
|
__ia64_nonlocal_goto:
|
|
{ .mmi
|
|
alloc r20 = ar.pfs, 3, 0, 0, 0
|
|
ld8 r12 = [in1], 8
|
|
mov.ret.sptk rp = in0, .L0
|
|
;;
|
|
}
|
|
{ .mmf
|
|
ld8 r16 = [in1], 8
|
|
mov r19 = ar.rsc
|
|
;;
|
|
}
|
|
{ .mmi
|
|
flushrs
|
|
ld8 r17 = [in1], 8
|
|
and r19 = 0x1c, r19
|
|
;;
|
|
}
|
|
{ .mmi
|
|
ld8 r18 = [in1]
|
|
mov ar.rsc = r19
|
|
or r19 = 0x3, r19
|
|
;;
|
|
}
|
|
{ .mmi
|
|
mov ar.bspstore = r16
|
|
;;
|
|
mov ar.rnat = r17
|
|
;;
|
|
}
|
|
{ .mmi
|
|
loadrs
|
|
invala
|
|
mov r15 = in2
|
|
;;
|
|
}
|
|
.L0: { .mib
|
|
mov ar.rsc = r19
|
|
mov ar.pfs = r18
|
|
br.ret.sptk.few rp
|
|
;;
|
|
}
|
|
.endp __ia64_nonlocal_goto
|
|
#endif
|
|
|
|
#ifdef L__restore_stack_nonlocal
|
|
// This is mostly the same as nonlocal_goto above.
|
|
// ??? This has not been tested yet.
|
|
|
|
// void __ia64_restore_stack_nonlocal(void *save_area)
|
|
|
|
.text
|
|
.align 16
|
|
.global __ia64_restore_stack_nonlocal
|
|
.proc __ia64_restore_stack_nonlocal
|
|
__ia64_restore_stack_nonlocal:
|
|
{ .mmf
|
|
alloc r20 = ar.pfs, 4, 0, 0, 0
|
|
ld8 r12 = [in0], 8
|
|
;;
|
|
}
|
|
{ .mmb
|
|
ld8 r16=[in0], 8
|
|
mov r19 = ar.rsc
|
|
;;
|
|
}
|
|
{ .mmi
|
|
flushrs
|
|
ld8 r17 = [in0], 8
|
|
and r19 = 0x1c, r19
|
|
;;
|
|
}
|
|
{ .mmf
|
|
ld8 r18 = [in0]
|
|
mov ar.rsc = r19
|
|
;;
|
|
}
|
|
{ .mmi
|
|
mov ar.bspstore = r16
|
|
;;
|
|
mov ar.rnat = r17
|
|
or r19 = 0x3, r19
|
|
;;
|
|
}
|
|
{ .mmf
|
|
loadrs
|
|
invala
|
|
;;
|
|
}
|
|
.L0: { .mib
|
|
mov ar.rsc = r19
|
|
mov ar.pfs = r18
|
|
br.ret.sptk.few rp
|
|
;;
|
|
}
|
|
.endp __ia64_restore_stack_nonlocal
|
|
#endif
|
|
|
|
#ifdef L__trampoline
|
|
// Implement the nested function trampoline. This is out of line
|
|
// so that we don't have to bother with flushing the icache, as
|
|
// well as making the on-stack trampoline smaller.
|
|
//
|
|
// The trampoline has the following form:
|
|
//
|
|
// +-------------------+ >
|
|
// TRAMP: | __ia64_trampoline | |
|
|
// +-------------------+ > fake function descriptor
|
|
// | TRAMP+16 | |
|
|
// +-------------------+ >
|
|
// | target descriptor |
|
|
// +-------------------+
|
|
// | static link |
|
|
// +-------------------+
|
|
|
|
.text
|
|
.align 16
|
|
.global __ia64_trampoline
|
|
.proc __ia64_trampoline
|
|
__ia64_trampoline:
|
|
{ .mmi
|
|
ld8 r2 = [r1], 8
|
|
;;
|
|
ld8 r15 = [r1]
|
|
}
|
|
{ .mmi
|
|
ld8 r3 = [r2], 8
|
|
;;
|
|
ld8 r1 = [r2]
|
|
mov b6 = r3
|
|
}
|
|
{ .bbb
|
|
br.sptk.many b6
|
|
;;
|
|
}
|
|
.endp __ia64_trampoline
|
|
#endif
|
|
|
|
// Thunks for backward compatibility.
|
|
#ifdef L_fixtfdi
|
|
.text
|
|
.align 16
|
|
.global __fixtfti
|
|
.proc __fixtfti
|
|
__fixtfti:
|
|
{ .bbb
|
|
br.sptk.many __fixxfti
|
|
;;
|
|
}
|
|
.endp __fixtfti
|
|
#endif
|
|
#ifdef L_fixunstfdi
|
|
.align 16
|
|
.global __fixunstfti
|
|
.proc __fixunstfti
|
|
__fixunstfti:
|
|
{ .bbb
|
|
br.sptk.many __fixunsxfti
|
|
;;
|
|
}
|
|
.endp __fixunstfti
|
|
#endif
|
|
#if L_floatditf
|
|
.align 16
|
|
.global __floattitf
|
|
.proc __floattitf
|
|
__floattitf:
|
|
{ .bbb
|
|
br.sptk.many __floattixf
|
|
;;
|
|
}
|
|
.endp __floattitf
|
|
#endif
|