561 lines
33 KiB
C
561 lines
33 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-mpi-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon mpi.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_MPI_DEFS_H__
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#define __CVMX_MPI_DEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
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static inline uint64_t CVMX_MPI_CFG_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
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cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070000001000ull);
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}
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#else
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#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
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(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
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(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8))) ||
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(OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 8))) ||
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(OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 8))) ||
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(OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 8)))))
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cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8;
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}
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#else
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#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
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static inline uint64_t CVMX_MPI_STS_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
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cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070000001008ull);
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}
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#else
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#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
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static inline uint64_t CVMX_MPI_TX_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
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cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070000001010ull);
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}
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#else
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#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
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#endif
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/**
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* cvmx_mpi_cfg
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*
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* SPI_MPI interface
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*
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*
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* Notes:
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* Some of the SPI/MPI pins are muxed with UART pins.
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* SPI_CLK : spi clock, dedicated pin
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* SPI_DI : spi input, shared with UART0_DCD_N/SPI_DI, enabled when MPI_CFG[ENABLE]=1
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* SPI_DO : spi output, mux to UART0_DTR_N/SPI_DO, enabled when MPI_CFG[ENABLE]=1
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* SPI_CS0_L : chips select 0, mux to BOOT_CE_N<6>/SPI_CS0_L pin, enabled when MPI_CFG[CSENA0]=1 and MPI_CFG[ENABLE]=1
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* SPI_CS1_L : chips select 1, mux to BOOT_CE_N<7>/SPI_CS1_L pin, enabled when MPI_CFG[CSENA1]=1 and MPI_CFG[ENABLE]=1
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*/
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union cvmx_mpi_cfg {
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uint64_t u64;
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struct cvmx_mpi_cfg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63 : 35;
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uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
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CLKDIV = Fsclk / (2 * Fspi_clk) */
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uint64_t csena3 : 1; /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin | NS
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1, UART1_RTS_L/SPI_CS3_L pin is SPI pin
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SPI_CS3_L drives UART1_RTS_L/SPI_CS3_L */
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uint64_t csena2 : 1; /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin | NS
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1, UART0_RTS_L/SPI_CS2_L pin is SPI pin
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SPI_CS2_L drives UART0_RTS_L/SPI_CS2_L */
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uint64_t csena1 : 1; /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin | NS
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1, BOOT_CE_N<7>/SPI_CS1_L pin is SPI pin
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SPI_CS1_L drives BOOT_CE_N<7>/SPI_CS1_L */
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uint64_t csena0 : 1; /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin | NS
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1, BOOT_CE_N<6>/SPI_CS0_L pin is SPI pin
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SPI_CS0_L drives BOOT_CE_N<6>/SPI_CS0_L */
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uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
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1, SPI_CS assert coincident with transaction
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NOTE: This control apply for 2 CSs */
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uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
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expected to be driving
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1, SPI_DO pin is tristated when not transmitting
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NOTE: only used when WIREOR==1 */
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uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
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commands. */
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uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
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1, CS is high asserted */
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uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
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1, CS is driven per MPI_TX intruction */
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uint64_t int_ena : 1; /**< If 0, polling is required | NS
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1, MPI engine interrupts X end of transaction */
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uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
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1, shift LSB first */
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uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
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SPI_DO pin is always driven
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1, SPI_DO/DI is all from SPI_DO pin (MPI)
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SPI_DO pin is tristated when not transmitting
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NOTE: if WIREOR==1, SPI_DI pin is not used by the
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MPI engine */
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uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
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completion of MPI transaction
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1, clock never idles, requires CS deassertion
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assertion between commands */
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uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
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1, SPI_CLK idles low, 1st transition is lo->hi */
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uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
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BOOT_CE_N<7:6>/SPI_CSx_L
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pins are UART/BOOT pins
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1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
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pins are SPI/MPI pins.
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BOOT_CE_N<6>/SPI_CS0_L is SPI pin if CSENA0=1
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BOOT_CE_N<7>/SPI_CS1_L is SPI pin if CSENA1=1 */
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#else
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uint64_t enable : 1;
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uint64_t idlelo : 1;
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uint64_t clk_cont : 1;
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uint64_t wireor : 1;
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uint64_t lsbfirst : 1;
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uint64_t int_ena : 1;
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uint64_t csena : 1;
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uint64_t cshi : 1;
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uint64_t idleclks : 2;
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uint64_t tritx : 1;
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uint64_t cslate : 1;
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uint64_t csena0 : 1;
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uint64_t csena1 : 1;
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uint64_t csena2 : 1;
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uint64_t csena3 : 1;
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uint64_t clkdiv : 13;
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uint64_t reserved_29_63 : 35;
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#endif
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} s;
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struct cvmx_mpi_cfg_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63 : 35;
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uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
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CLKDIV = Feclk / (2 * Fsclk) */
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uint64_t reserved_12_15 : 4;
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uint64_t cslate : 1; /**< If 0, MPI_CS asserts 1/2 SCLK before transaction
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1, MPI_CS assert coincident with transaction
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NOTE: only used if CSENA == 1 */
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uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
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expected to be driving
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1, MPI_TX pin is tristated when not transmitting
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NOTE: only used when WIREOR==1 */
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uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
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commands. */
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uint64_t cshi : 1; /**< If 0, CS is low asserted
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1, CS is high asserted */
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uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
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1, CS is driven per MPI_TX intruction */
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uint64_t int_ena : 1; /**< If 0, polling is required
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1, MPI engine interrupts X end of transaction */
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uint64_t lsbfirst : 1; /**< If 0, shift MSB first
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1, shift LSB first */
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uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
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MPI_TX pin is always driven
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1, MPI_TX/RX is all from MPI_TX pin (MPI)
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MPI_TX pin is tristated when not transmitting
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NOTE: if WIREOR==1, MPI_RX pin is not used by the
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MPI engine */
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uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
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completion of MPI transaction
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1, clock never idles, requires CS deassertion
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assertion between commands */
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uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
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1, MPI_CLK idles low, 1st transition is lo->hi */
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uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
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1, MPI_CLK, MPI_CS, and MPI_TX are driven */
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#else
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uint64_t enable : 1;
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uint64_t idlelo : 1;
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uint64_t clk_cont : 1;
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uint64_t wireor : 1;
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uint64_t lsbfirst : 1;
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uint64_t int_ena : 1;
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uint64_t csena : 1;
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uint64_t cshi : 1;
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uint64_t idleclks : 2;
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uint64_t tritx : 1;
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uint64_t cslate : 1;
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uint64_t reserved_12_15 : 4;
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uint64_t clkdiv : 13;
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uint64_t reserved_29_63 : 35;
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#endif
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} cn30xx;
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struct cvmx_mpi_cfg_cn31xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63 : 35;
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uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
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CLKDIV = Feclk / (2 * Fsclk) */
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uint64_t reserved_11_15 : 5;
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uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
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expected to be driving
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1, MPI_TX pin is tristated when not transmitting
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NOTE: only used when WIREOR==1 */
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uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
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commands. */
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uint64_t cshi : 1; /**< If 0, CS is low asserted
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1, CS is high asserted */
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uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
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1, CS is driven per MPI_TX intruction */
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uint64_t int_ena : 1; /**< If 0, polling is required
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1, MPI engine interrupts X end of transaction */
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uint64_t lsbfirst : 1; /**< If 0, shift MSB first
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1, shift LSB first */
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uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
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MPI_TX pin is always driven
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1, MPI_TX/RX is all from MPI_TX pin (MPI)
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MPI_TX pin is tristated when not transmitting
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NOTE: if WIREOR==1, MPI_RX pin is not used by the
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MPI engine */
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uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
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completion of MPI transaction
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1, clock never idles, requires CS deassertion
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assertion between commands */
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uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
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1, MPI_CLK idles low, 1st transition is lo->hi */
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uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
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1, MPI_CLK, MPI_CS, and MPI_TX are driven */
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#else
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uint64_t enable : 1;
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uint64_t idlelo : 1;
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uint64_t clk_cont : 1;
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uint64_t wireor : 1;
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uint64_t lsbfirst : 1;
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uint64_t int_ena : 1;
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uint64_t csena : 1;
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uint64_t cshi : 1;
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uint64_t idleclks : 2;
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uint64_t tritx : 1;
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uint64_t reserved_11_15 : 5;
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uint64_t clkdiv : 13;
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uint64_t reserved_29_63 : 35;
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#endif
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} cn31xx;
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struct cvmx_mpi_cfg_cn30xx cn50xx;
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struct cvmx_mpi_cfg_cn61xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63 : 35;
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uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
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CLKDIV = Fsclk / (2 * Fspi_clk) */
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uint64_t reserved_14_15 : 2;
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uint64_t csena1 : 1; /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin | NS
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1, BOOT_CE_N<7>/SPI_CS1_L pin is SPI pin
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SPI_CS1_L drives BOOT_CE_N<7>/SPI_CS1_L */
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uint64_t csena0 : 1; /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin | NS
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1, BOOT_CE_N<6>/SPI_CS0_L pin is SPI pin
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SPI_CS0_L drives BOOT_CE_N<6>/SPI_CS0_L */
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uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
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1, SPI_CS assert coincident with transaction
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NOTE: This control apply for 2 CSs */
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uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
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expected to be driving
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1, SPI_DO pin is tristated when not transmitting
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NOTE: only used when WIREOR==1 */
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uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
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commands. */
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uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
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1, CS is high asserted */
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uint64_t reserved_6_6 : 1;
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uint64_t int_ena : 1; /**< If 0, polling is required | NS
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1, MPI engine interrupts X end of transaction */
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uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
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1, shift LSB first */
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uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
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SPI_DO pin is always driven
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1, SPI_DO/DI is all from SPI_DO pin (MPI)
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SPI_DO pin is tristated when not transmitting
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NOTE: if WIREOR==1, SPI_DI pin is not used by the
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MPI engine */
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uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
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completion of MPI transaction
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1, clock never idles, requires CS deassertion
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assertion between commands */
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uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
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1, SPI_CLK idles low, 1st transition is lo->hi */
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uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
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BOOT_CE_N<7:6>/SPI_CSx_L
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pins are UART/BOOT pins
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1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
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pins are SPI/MPI pins.
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BOOT_CE_N<6>/SPI_CS0_L is SPI pin if CSENA0=1
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BOOT_CE_N<7>/SPI_CS1_L is SPI pin if CSENA1=1 */
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#else
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uint64_t enable : 1;
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uint64_t idlelo : 1;
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uint64_t clk_cont : 1;
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uint64_t wireor : 1;
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uint64_t lsbfirst : 1;
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uint64_t int_ena : 1;
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uint64_t reserved_6_6 : 1;
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uint64_t cshi : 1;
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uint64_t idleclks : 2;
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uint64_t tritx : 1;
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uint64_t cslate : 1;
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uint64_t csena0 : 1;
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uint64_t csena1 : 1;
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uint64_t reserved_14_15 : 2;
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uint64_t clkdiv : 13;
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uint64_t reserved_29_63 : 35;
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#endif
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} cn61xx;
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struct cvmx_mpi_cfg_cn66xx {
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#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_29_63 : 35;
|
|
uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
|
|
CLKDIV = Fsclk / (2 * Fspi_clk) */
|
|
uint64_t csena3 : 1; /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin | NS
|
|
1, UART1_RTS_L/SPI_CS3_L pin is SPI pin
|
|
SPI_CS3_L drives UART1_RTS_L/SPI_CS3_L */
|
|
uint64_t csena2 : 1; /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin | NS
|
|
1, UART0_RTS_L/SPI_CS2_L pin is SPI pin
|
|
SPI_CS2_L drives UART0_RTS_L/SPI_CS2_L */
|
|
uint64_t reserved_12_13 : 2;
|
|
uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
|
|
1, SPI_CS assert coincident with transaction
|
|
NOTE: This control apply for 4 CSs */
|
|
uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
|
|
expected to be driving
|
|
1, SPI_DO pin is tristated when not transmitting
|
|
NOTE: only used when WIREOR==1 */
|
|
uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
|
|
commands. */
|
|
uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
|
|
1, CS is high asserted */
|
|
uint64_t reserved_6_6 : 1;
|
|
uint64_t int_ena : 1; /**< If 0, polling is required | NS
|
|
1, MPI engine interrupts X end of transaction */
|
|
uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
|
|
1, shift LSB first */
|
|
uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
|
|
SPI_DO pin is always driven
|
|
1, SPI_DO/DI is all from SPI_DO pin (MPI)
|
|
SPI_DO pin is tristated when not transmitting
|
|
NOTE: if WIREOR==1, SPI_DI pin is not used by the
|
|
MPI engine */
|
|
uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
|
|
completion of MPI transaction
|
|
1, clock never idles, requires CS deassertion
|
|
assertion between commands */
|
|
uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
|
|
1, SPI_CLK idles low, 1st transition is lo->hi */
|
|
uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
|
|
UART0_RTS_L/SPI_CS2_L, UART1_RTS_L/SPI_CS3_L
|
|
pins are UART pins
|
|
1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
|
|
pins are SPI/MPI pins.
|
|
UART0_RTS_L/SPI_CS2_L is SPI pin if CSENA2=1
|
|
UART1_RTS_L/SPI_CS3_L is SPI pin if CSENA3=1 */
|
|
#else
|
|
uint64_t enable : 1;
|
|
uint64_t idlelo : 1;
|
|
uint64_t clk_cont : 1;
|
|
uint64_t wireor : 1;
|
|
uint64_t lsbfirst : 1;
|
|
uint64_t int_ena : 1;
|
|
uint64_t reserved_6_6 : 1;
|
|
uint64_t cshi : 1;
|
|
uint64_t idleclks : 2;
|
|
uint64_t tritx : 1;
|
|
uint64_t cslate : 1;
|
|
uint64_t reserved_12_13 : 2;
|
|
uint64_t csena2 : 1;
|
|
uint64_t csena3 : 1;
|
|
uint64_t clkdiv : 13;
|
|
uint64_t reserved_29_63 : 35;
|
|
#endif
|
|
} cn66xx;
|
|
struct cvmx_mpi_cfg_cn61xx cnf71xx;
|
|
};
|
|
typedef union cvmx_mpi_cfg cvmx_mpi_cfg_t;
|
|
|
|
/**
|
|
* cvmx_mpi_dat#
|
|
*/
|
|
union cvmx_mpi_datx {
|
|
uint64_t u64;
|
|
struct cvmx_mpi_datx_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_8_63 : 56;
|
|
uint64_t data : 8; /**< Data to transmit/received | NS */
|
|
#else
|
|
uint64_t data : 8;
|
|
uint64_t reserved_8_63 : 56;
|
|
#endif
|
|
} s;
|
|
struct cvmx_mpi_datx_s cn30xx;
|
|
struct cvmx_mpi_datx_s cn31xx;
|
|
struct cvmx_mpi_datx_s cn50xx;
|
|
struct cvmx_mpi_datx_s cn61xx;
|
|
struct cvmx_mpi_datx_s cn66xx;
|
|
struct cvmx_mpi_datx_s cnf71xx;
|
|
};
|
|
typedef union cvmx_mpi_datx cvmx_mpi_datx_t;
|
|
|
|
/**
|
|
* cvmx_mpi_sts
|
|
*/
|
|
union cvmx_mpi_sts {
|
|
uint64_t u64;
|
|
struct cvmx_mpi_sts_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_13_63 : 51;
|
|
uint64_t rxnum : 5; /**< Number of bytes written for transaction | NS */
|
|
uint64_t reserved_1_7 : 7;
|
|
uint64_t busy : 1; /**< If 0, no MPI transaction in progress | NS
|
|
1, MPI engine is processing a transaction */
|
|
#else
|
|
uint64_t busy : 1;
|
|
uint64_t reserved_1_7 : 7;
|
|
uint64_t rxnum : 5;
|
|
uint64_t reserved_13_63 : 51;
|
|
#endif
|
|
} s;
|
|
struct cvmx_mpi_sts_s cn30xx;
|
|
struct cvmx_mpi_sts_s cn31xx;
|
|
struct cvmx_mpi_sts_s cn50xx;
|
|
struct cvmx_mpi_sts_s cn61xx;
|
|
struct cvmx_mpi_sts_s cn66xx;
|
|
struct cvmx_mpi_sts_s cnf71xx;
|
|
};
|
|
typedef union cvmx_mpi_sts cvmx_mpi_sts_t;
|
|
|
|
/**
|
|
* cvmx_mpi_tx
|
|
*/
|
|
union cvmx_mpi_tx {
|
|
uint64_t u64;
|
|
struct cvmx_mpi_tx_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_22_63 : 42;
|
|
uint64_t csid : 2; /**< Which CS to assert for this transaction | NS */
|
|
uint64_t reserved_17_19 : 3;
|
|
uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done | NS
|
|
1, leave CS asserted after transactrion is done */
|
|
uint64_t reserved_13_15 : 3;
|
|
uint64_t txnum : 5; /**< Number of bytes to transmit | NS */
|
|
uint64_t reserved_5_7 : 3;
|
|
uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) | NS */
|
|
#else
|
|
uint64_t totnum : 5;
|
|
uint64_t reserved_5_7 : 3;
|
|
uint64_t txnum : 5;
|
|
uint64_t reserved_13_15 : 3;
|
|
uint64_t leavecs : 1;
|
|
uint64_t reserved_17_19 : 3;
|
|
uint64_t csid : 2;
|
|
uint64_t reserved_22_63 : 42;
|
|
#endif
|
|
} s;
|
|
struct cvmx_mpi_tx_cn30xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_17_63 : 47;
|
|
uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done
|
|
1, leave CS asserted after transactrion is done */
|
|
uint64_t reserved_13_15 : 3;
|
|
uint64_t txnum : 5; /**< Number of bytes to transmit */
|
|
uint64_t reserved_5_7 : 3;
|
|
uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) */
|
|
#else
|
|
uint64_t totnum : 5;
|
|
uint64_t reserved_5_7 : 3;
|
|
uint64_t txnum : 5;
|
|
uint64_t reserved_13_15 : 3;
|
|
uint64_t leavecs : 1;
|
|
uint64_t reserved_17_63 : 47;
|
|
#endif
|
|
} cn30xx;
|
|
struct cvmx_mpi_tx_cn30xx cn31xx;
|
|
struct cvmx_mpi_tx_cn30xx cn50xx;
|
|
struct cvmx_mpi_tx_cn61xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_21_63 : 43;
|
|
uint64_t csid : 1; /**< Which CS to assert for this transaction | NS */
|
|
uint64_t reserved_17_19 : 3;
|
|
uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done | NS
|
|
1, leave CS asserted after transactrion is done */
|
|
uint64_t reserved_13_15 : 3;
|
|
uint64_t txnum : 5; /**< Number of bytes to transmit | NS */
|
|
uint64_t reserved_5_7 : 3;
|
|
uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) | NS */
|
|
#else
|
|
uint64_t totnum : 5;
|
|
uint64_t reserved_5_7 : 3;
|
|
uint64_t txnum : 5;
|
|
uint64_t reserved_13_15 : 3;
|
|
uint64_t leavecs : 1;
|
|
uint64_t reserved_17_19 : 3;
|
|
uint64_t csid : 1;
|
|
uint64_t reserved_21_63 : 43;
|
|
#endif
|
|
} cn61xx;
|
|
struct cvmx_mpi_tx_s cn66xx;
|
|
struct cvmx_mpi_tx_cn61xx cnf71xx;
|
|
};
|
|
typedef union cvmx_mpi_tx cvmx_mpi_tx_t;
|
|
|
|
#endif
|