320 lines
8.7 KiB
C
320 lines
8.7 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Broadcom ChipCommon driver.
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*
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* With the exception of some very early chipsets, the ChipCommon core
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* has been included in all HND SoCs and chipsets based on the siba(4)
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* and bcma(4) interconnects, providing a common interface to chipset
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* identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO,
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* flash, etc.
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <dev/bhnd/bhnd.h>
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#include "chipcreg.h"
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#include "chipcvar.h"
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devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */
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static const struct resource_spec chipc_rspec[CHIPC_MAX_RSPEC] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, -1, 0 }
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};
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/* Supported device identifiers */
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static const struct chipc_device {
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uint16_t device;
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} chipc_devices[] = {
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{ BHND_COREID_CC },
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{ BHND_COREID_INVALID }
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};
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/* Device quirks table */
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static struct bhnd_device_quirk chipc_quirks[] = {
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BHND_QUIRK_HWREV_RANGE (0, 21, CHIPC_QUIRK_ALWAYS_HAS_SPROM),
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BHND_QUIRK_HWREV_EQ (22, CHIPC_QUIRK_SPROM_CHECK_CST_R22),
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BHND_QUIRK_HWREV_RANGE (23, 31, CHIPC_QUIRK_SPROM_CHECK_CST_R23),
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BHND_QUIRK_HWREV_GTE (35, CHIPC_QUIRK_SUPPORTS_NFLASH),
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BHND_QUIRK_HWREV_END
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};
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/* quirk and capability flag convenience macros */
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#define CHIPC_QUIRK(_sc, _name) \
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((_sc)->quirks & CHIPC_QUIRK_ ## _name)
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#define CHIPC_CAP(_sc, _name) \
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((_sc)->caps & CHIPC_ ## _name)
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#define CHIPC_ASSERT_QUIRK(_sc, name) \
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KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
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#define CHIPC_ASSERT_CAP(_sc, name) \
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KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
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static int
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chipc_probe(device_t dev)
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{
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const struct chipc_device *id;
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for (id = chipc_devices; id->device != BHND_COREID_INVALID; id++)
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{
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if (bhnd_get_vendor(dev) == BHND_MFGID_BCM &&
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bhnd_get_device(dev) == id->device)
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{
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bhnd_set_generic_core_desc(dev);
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return (BUS_PROBE_DEFAULT);
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}
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}
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return (ENXIO);
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}
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static int
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chipc_attach(device_t dev)
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{
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struct bhnd_device_quirk *dq;
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struct chipc_softc *sc;
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bhnd_addr_t enum_addr;
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uint32_t ccid_reg;
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uint8_t chip_type;
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int error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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/* Allocate bus resources */
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memcpy(sc->rspec, chipc_rspec, sizeof(sc->rspec));
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if ((error = bhnd_alloc_resources(dev, sc->rspec, sc->res)))
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return (error);
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sc->core = sc->res[0];
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/* Fetch our chipset identification data */
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ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID);
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chip_type = CHIPC_GET_ATTR(ccid_reg, ID_BUS);
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switch (chip_type) {
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case BHND_CHIPTYPE_SIBA:
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/* enumeration space starts at the ChipCommon register base. */
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enum_addr = rman_get_start(sc->core->res);
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break;
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case BHND_CHIPTYPE_BCMA:
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case BHND_CHIPTYPE_BCMA_ALT:
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enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR);
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break;
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default:
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device_printf(dev, "unsupported chip type %hhu\n", chip_type);
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error = ENODEV;
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goto cleanup;
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}
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sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr);
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/* Fetch capability and status register values */
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sc->caps = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
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sc->cst = bhnd_bus_read_4(sc->core, CHIPC_CHIPST);
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/* Populate the set of applicable quirk flags */
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sc->quirks = 0;
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for (dq = chipc_quirks; dq->quirks != 0; dq++) {
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if (bhnd_hwrev_matches(bhnd_get_hwrev(dev), &dq->hwrev))
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sc->quirks |= dq->quirks;
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}
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// TODO
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switch (bhnd_chipc_nvram_src(dev)) {
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case BHND_NVRAM_SRC_CIS:
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device_printf(dev, "NVRAM source: CIS\n");
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break;
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case BHND_NVRAM_SRC_SPROM:
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device_printf(dev, "NVRAM source: SPROM\n");
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break;
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case BHND_NVRAM_SRC_OTP:
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device_printf(dev, "NVRAM source: OTP\n");
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break;
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case BHND_NVRAM_SRC_NFLASH:
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device_printf(dev, "NVRAM source: NFLASH\n");
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break;
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case BHND_NVRAM_SRC_NONE:
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device_printf(dev, "NVRAM source: NONE\n");
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break;
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}
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return (0);
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cleanup:
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bhnd_release_resources(dev, sc->rspec, sc->res);
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return (error);
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}
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static int
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chipc_detach(device_t dev)
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{
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struct chipc_softc *sc;
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sc = device_get_softc(dev);
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bhnd_release_resources(dev, sc->rspec, sc->res);
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return (0);
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}
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static int
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chipc_suspend(device_t dev)
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{
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return (0);
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}
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static int
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chipc_resume(device_t dev)
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{
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return (0);
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}
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/**
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* Use device-specific ChipStatus flags to determine the preferred NVRAM
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* data source.
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*/
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static bhnd_nvram_src_t
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chipc_nvram_src_chipst(struct chipc_softc *sc)
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{
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uint8_t nvram_sel;
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CHIPC_ASSERT_QUIRK(sc, SPROM_CHECK_CHIPST);
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if (CHIPC_QUIRK(sc, SPROM_CHECK_CST_R22)) {
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// TODO: On these devices, the official driver code always
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// assumes SPROM availability if CHIPC_CST_OTP_SEL is not
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// set; we must review against the actual behavior of our
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// BCM4312 hardware
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nvram_sel = CHIPC_GET_ATTR(sc->cst, CST_SPROM_OTP_SEL_R22);
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} else if (CHIPC_QUIRK(sc, SPROM_CHECK_CST_R23)) {
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nvram_sel = CHIPC_GET_ATTR(sc->cst, CST_SPROM_OTP_SEL_R23);
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} else {
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panic("invalid CST OTP/SPROM chipc quirk flags");
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}
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device_printf(sc->dev, "querying chipst for 0x%x, 0x%x\n", sc->ccid.chip_id, sc->cst);
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switch (nvram_sel) {
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case CHIPC_CST_DEFCIS_SEL:
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return (BHND_NVRAM_SRC_CIS);
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case CHIPC_CST_SPROM_SEL:
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case CHIPC_CST_OTP_PWRDN:
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return (BHND_NVRAM_SRC_SPROM);
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case CHIPC_CST_OTP_SEL:
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return (BHND_NVRAM_SRC_OTP);
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default:
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device_printf(sc->dev, "unrecognized OTP/SPROM type 0x%hhx",
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nvram_sel);
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return (BHND_NVRAM_SRC_NONE);
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}
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}
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/**
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* Determine the preferred NVRAM data source.
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*/
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static bhnd_nvram_src_t
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chipc_nvram_src(device_t dev)
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{
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struct chipc_softc *sc;
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uint32_t srom_ctrl;
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sc = device_get_softc(dev);
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/* Very early devices always included a SPROM */
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if (CHIPC_QUIRK(sc, ALWAYS_HAS_SPROM))
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return (BHND_NVRAM_SRC_SPROM);
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/* Most other early devices require checking ChipStatus flags */
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if (CHIPC_QUIRK(sc, SPROM_CHECK_CHIPST))
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return (chipc_nvram_src_chipst(sc));
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/*
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* Later chipset revisions standardized the NVRAM capability flags and
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* register interfaces.
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*
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* We check for hardware presence in order of precedence. For example,
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* SPROM is is always used in preference to internal OTP if found.
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*/
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if (CHIPC_CAP(sc, CAP_SPROM)) {
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srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
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if (srom_ctrl & CHIPC_SRC_PRESENT)
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return (BHND_NVRAM_SRC_SPROM);
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}
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/* Check for OTP */
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if (CHIPC_CAP(sc, CAP_OTP_SIZE))
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return (BHND_NVRAM_SRC_OTP);
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/*
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* Finally, Northstar chipsets (and possibly other chipsets?) support
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* external NAND flash.
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*/
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if (CHIPC_QUIRK(sc, SUPPORTS_NFLASH) && CHIPC_CAP(sc, CAP_NFLASH))
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return (BHND_NVRAM_SRC_NFLASH);
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/* No NVRAM hardware capability declared */
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return (BHND_NVRAM_SRC_NONE);
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}
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static device_method_t chipc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, chipc_probe),
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DEVMETHOD(device_attach, chipc_attach),
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DEVMETHOD(device_detach, chipc_detach),
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DEVMETHOD(device_suspend, chipc_suspend),
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DEVMETHOD(device_resume, chipc_resume),
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/* ChipCommon interface */
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DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc));
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DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0);
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MODULE_VERSION(bhnd_chipc, 1);
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