9c6d6488fa
we will import a newer version of the Linux code so the linuxkpi was not used. This is still missing 10G support, and multicast has not been tested. Reviewed by: gnn Obtained from: ABT Systems Ltd Sponsored by: SoftIron Inc Differential Revision: https://reviews.freebsd.org/D8549
189 lines
5.0 KiB
C
189 lines
5.0 KiB
C
/*-
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* Copyright (c) 2016,2017 SoftIron Inc.
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* All rights reserved.
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*
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* This software was developed by Andrew Turner under
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* the sponsorship of SoftIron Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _XGBE_OSDEP_H_
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#define _XGBE_OSDEP_H_
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/mutex.h>
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#include <sys/socket.h>
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#include <sys/sx.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h>
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typedef uint8_t u8;
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typedef uint16_t u16;
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typedef uint32_t __le32;
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typedef uint32_t u32;
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typedef uint64_t u64;
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typedef struct {
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struct mtx lock;
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} spinlock_t;
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static inline void
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spin_lock_init(spinlock_t *spinlock)
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{
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mtx_init(&spinlock->lock, "axgbe_spin", NULL, MTX_DEF);
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}
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#define spin_lock_irqsave(spinlock, flags) \
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do { \
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(flags) = intr_disable(); \
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mtx_lock(&(spinlock)->lock); \
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} while (0)
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#define spin_unlock_irqrestore(spinlock, flags) \
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do { \
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mtx_unlock(&(spinlock)->lock); \
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intr_restore(flags); \
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} while (0)
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#define BIT(pos) (1ul << pos)
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static inline void
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clear_bit(int pos, unsigned long *p)
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{
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atomic_clear_long(p, 1ul << pos);
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}
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static inline int
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test_bit(int pos, unsigned long *p)
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{
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unsigned long val;
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val = *p;
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return ((val & 1ul << pos) != 0);
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}
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static inline void
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set_bit(int pos, unsigned long *p)
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{
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atomic_set_long(p, 1ul << pos);
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}
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#define lower_32_bits(x) ((x) & 0xffffffffu)
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#define upper_32_bits(x) (((x) >> 32) & 0xffffffffu)
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#define cpu_to_le32(x) le32toh(x)
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#define le32_to_cpu(x) htole32(x)
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MALLOC_DECLARE(M_AXGBE);
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#define ADVERTISED_Pause 0x01
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#define ADVERTISED_Asym_Pause 0x02
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#define ADVERTISED_Autoneg 0x04
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#define ADVERTISED_Backplane 0x08
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#define ADVERTISED_10000baseKR_Full 0x10
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#define ADVERTISED_2500baseX_Full 0x20
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#define ADVERTISED_1000baseKX_Full 0x40
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#define AUTONEG_DISABLE 0
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#define AUTONEG_ENABLE 1
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#define DUPLEX_UNKNOWN 1
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#define DUPLEX_FULL 2
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#define SPEED_UNKNOWN 1
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#define SPEED_10000 2
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#define SPEED_2500 3
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#define SPEED_1000 4
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#define SUPPORTED_Autoneg 0x01
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#define SUPPORTED_Pause 0x02
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#define SUPPORTED_Asym_Pause 0x04
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#define SUPPORTED_Backplane 0x08
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#define SUPPORTED_10000baseKR_Full 0x10
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#define SUPPORTED_1000baseKX_Full 0x20
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#define SUPPORTED_2500baseX_Full 0x40
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#define SUPPORTED_10000baseR_FEC 0x80
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#define BMCR_SPEED100 0x2000
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#define MDIO_MMD_PMAPMD 1
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#define MDIO_MMD_PCS 3
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#define MDIO_MMD_AN 7
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#define MDIO_PMA_10GBR_FECABLE 170
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#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001
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#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002
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#define MII_ADDR_C45 (1<<30)
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#define MDIO_CTRL1 0x00 /* MII_BMCR */
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#define MDIO_CTRL1_RESET 0x8000 /* BMCR_RESET */
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#define MDIO_CTRL1_SPEEDSELEXT 0x2040 /* BMCR_SPEED1000|BMCR_SPEED100*/
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#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x3c)
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#define MDIO_AN_CTRL1_ENABLE 0x1000 /* BMCR_AUTOEN */
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#define MDIO_CTRL1_LPOWER 0x0800 /* BMCR_PDOWN */
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#define MDIO_AN_CTRL1_RESTART 0x0200 /* BMCR_STARTNEG */
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#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
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#define MDIO_STAT1 1 /* MII_BMSR */
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#define MDIO_STAT1_LSTATUS 0x0004 /* BMSR_LINK */
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#define MDIO_CTRL2 0x07
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#define MDIO_PCS_CTRL2_10GBR 0x0000
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#define MDIO_PCS_CTRL2_10GBX 0x0001
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#define MDIO_PCS_CTRL2_TYPE 0x0003
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#define MDIO_AN_ADVERTISE 16
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#define MDIO_AN_LPA 19
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#define ETH_ALEN ETHER_ADDR_LEN
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#define ETH_HLEN ETHER_HDR_LEN
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#define ETH_FCS_LEN 4
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#define VLAN_HLEN ETHER_VLAN_ENCAP_LEN
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#define ARRAY_SIZE(x) nitems(x)
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#define BITS_PER_LONG (sizeof(long) * CHAR_BIT)
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#define BITS_TO_LONGS(n) howmany((n), BITS_PER_LONG)
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#define NSEC_PER_SEC 1000000000ul
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#define min_t(t, a, b) MIN((t)(a), (t)(b))
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#define max_t(t, a, b) MAX((t)(a), (t)(b))
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#endif /* _XGBE_OSDEP_H_ */
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