Tycho Nightingale 76b3c718be When ICW1 is issued the edge sense circuit is reset which means that ... following an initialization a low-to-high transistion is necesary to generate an interrupt. Reviewed by: neel		2015-03-06 02:05:45 +00:00
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acpica	don't set CR4 PSE bit on amd64	2014-07-23 15:53:29 +00:00
amd64	Supposed fix for some SandyBridge mobile CPUs hang on AP startup when	2015-02-28 20:37:38 +00:00
conf	Implement interface to create SR-IOV Virtual Functions	2015-03-01 00:40:09 +00:00
ia32	Do not qualify the mcontext_t *mcp argument for set_mcontext(9) as	2015-01-31 21:43:46 +00:00
include	Add x2APIC support. Enable it by default if CPU is capable. The	2015-02-09 21:00:56 +00:00
linux32	Regen after r276508, r276509.	2015-01-01 18:43:31 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
vmm	When ICW1 is issued the edge sense circuit is reset which means that	2015-03-06 02:05:45 +00:00
Makefile