51d163d3e9
simplifies certain device attachments (Kauai ATA, for instance), and makes possible others on new hardware. On G5 systems, there are several otherwise standard PCI devices (Serverworks SATA) that will not allow their interrupt properties to be written, so this information must be supplied directly from Open Firmware. Obtained from: sparc64
423 lines
9.8 KiB
C
423 lines
9.8 KiB
C
/*
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* Copyright (c) 2006 Maxim Sobolev <sobomax@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/uio.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <machine/bus.h>
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#include <machine/md_var.h>
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#include <machine/pio.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <dev/powermac_nvram/powermac_nvramvar.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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/*
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* Device interface.
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*/
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static int powermac_nvram_probe(device_t);
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static int powermac_nvram_attach(device_t);
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static int powermac_nvram_detach(device_t);
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/* Helper functions */
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static int powermac_nvram_check(void *data);
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static int chrp_checksum(int sum, uint8_t *, uint8_t *);
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static uint32_t adler_checksum(uint8_t *, int);
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static int erase_bank(device_t, uint8_t *);
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static int write_bank(device_t, uint8_t *, uint8_t *);
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/*
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* Driver methods.
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*/
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static device_method_t powermac_nvram_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, powermac_nvram_probe),
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DEVMETHOD(device_attach, powermac_nvram_attach),
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DEVMETHOD(device_detach, powermac_nvram_detach),
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{ 0, 0 }
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};
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static driver_t powermac_nvram_driver = {
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"powermac_nvram",
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powermac_nvram_methods,
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sizeof(struct powermac_nvram_softc)
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};
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static devclass_t powermac_nvram_devclass;
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DRIVER_MODULE(powermac_nvram, nexus, powermac_nvram_driver, powermac_nvram_devclass, 0, 0);
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/*
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* Cdev methods.
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*/
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#define NVRAM_UNIT(dev) dev2unit(dev)
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#define NVRAM_SOFTC(unit) ((struct powermac_nvram_softc *) \
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devclass_get_softc(powermac_nvram_devclass, unit))
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static d_open_t powermac_nvram_open;
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static d_close_t powermac_nvram_close;
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static d_read_t powermac_nvram_read;
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static d_write_t powermac_nvram_write;
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static struct cdevsw powermac_nvram_cdevsw = {
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.d_version = D_VERSION,
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.d_flags = D_NEEDGIANT,
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.d_open = powermac_nvram_open,
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.d_close = powermac_nvram_close,
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.d_read = powermac_nvram_read,
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.d_write = powermac_nvram_write,
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.d_name = "powermac_nvram",
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};
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static int
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powermac_nvram_probe(device_t dev)
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{
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const char *type, *compatible;
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type = ofw_bus_get_type(dev);
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compatible = ofw_bus_get_compat(dev);
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if (type == NULL || compatible == NULL)
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return ENXIO;
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if (strcmp(type, "nvram") != 0 || strcmp(compatible, "amd-0137") != 0)
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return ENXIO;
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device_set_desc(dev, "Apple NVRAM");
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return 0;
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}
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static int
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powermac_nvram_attach(device_t dev)
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{
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struct powermac_nvram_softc *sc;
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phandle_t node;
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u_int32_t reg[2];
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int gen0, gen1;
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
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return ENXIO;
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sc->sc_dev = dev;
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sc->sc_node = node;
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sc->sc_bank0 = (vm_offset_t)pmap_mapdev(reg[0], NVRAM_SIZE * 2);
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sc->sc_bank1 = sc->sc_bank0 + NVRAM_SIZE;
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gen0 = powermac_nvram_check((void *)sc->sc_bank0);
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gen1 = powermac_nvram_check((void *)sc->sc_bank1);
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if (gen0 == -1 && gen1 == -1) {
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if ((void *)sc->sc_bank0 != NULL)
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pmap_unmapdev(sc->sc_bank0, NVRAM_SIZE * 2);
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device_printf(dev, "both banks appear to be corrupt\n");
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return ENXIO;
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}
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device_printf(dev, "bank0 generation %d, bank1 generation %d\n",
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gen0, gen1);
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sc->sc_bank = (gen0 > gen1) ? sc->sc_bank0 : sc->sc_bank1;
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bcopy((void *)sc->sc_bank, (void *)sc->sc_data, NVRAM_SIZE);
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sc->sc_cdev = make_dev(&powermac_nvram_cdevsw, 0, 0, 0, 0600,
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"powermac_nvram");
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return 0;
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}
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static int
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powermac_nvram_detach(device_t dev)
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{
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struct powermac_nvram_softc *sc;
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sc = device_get_softc(dev);
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if ((void *)sc->sc_bank0 != NULL)
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pmap_unmapdev(sc->sc_bank0, NVRAM_SIZE * 2);
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if (sc->sc_cdev != NULL)
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destroy_dev(sc->sc_cdev);
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return 0;
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}
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static int
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powermac_nvram_open(struct cdev *dev, int flags, int fmt, struct thread *td)
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{
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struct powermac_nvram_softc *sc;
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sc = NVRAM_SOFTC(NVRAM_UNIT(dev));
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if (sc->sc_isopen)
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return EBUSY;
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sc->sc_isopen = 1;
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sc->sc_rpos = sc->sc_wpos = 0;
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return 0;
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}
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static int
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powermac_nvram_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
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{
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struct powermac_nvram_softc *sc;
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struct core99_header *header;
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vm_offset_t bank;
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sc = NVRAM_SOFTC(NVRAM_UNIT(dev));
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if (sc->sc_wpos != sizeof(sc->sc_data)) {
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/* Short write, restore in-memory copy */
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bcopy((void *)sc->sc_bank, (void *)sc->sc_data, NVRAM_SIZE);
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sc->sc_isopen = 0;
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return 0;
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}
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header = (struct core99_header *)sc->sc_data;
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header->generation = ((struct core99_header *)sc->sc_bank)->generation;
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header->generation++;
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header->chrp_header.signature = CORE99_SIGNATURE;
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header->adler_checksum =
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adler_checksum((uint8_t *)&(header->generation),
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NVRAM_SIZE - offsetof(struct core99_header, generation));
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header->chrp_header.chrp_checksum = chrp_checksum(header->chrp_header.signature,
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(uint8_t *)&(header->chrp_header.length),
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(uint8_t *)&(header->adler_checksum));
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bank = (sc->sc_bank == sc->sc_bank0) ? sc->sc_bank1 : sc->sc_bank0;
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if (erase_bank(sc->sc_dev, (uint8_t *)bank) != 0 ||
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write_bank(sc->sc_dev, (uint8_t *)bank, sc->sc_data) != 0) {
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sc->sc_isopen = 0;
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return ENOSPC;
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}
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sc->sc_bank = bank;
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sc->sc_isopen = 0;
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return 0;
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}
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static int
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powermac_nvram_read(struct cdev *dev, struct uio *uio, int ioflag)
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{
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int rv, amnt, data_available;
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struct powermac_nvram_softc *sc;
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sc = NVRAM_SOFTC(NVRAM_UNIT(dev));
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rv = 0;
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while (uio->uio_resid > 0) {
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data_available = sizeof(sc->sc_data) - sc->sc_rpos;
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if (data_available > 0) {
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amnt = MIN(uio->uio_resid, data_available);
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rv = uiomove((void *)(sc->sc_data + sc->sc_rpos),
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amnt, uio);
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if (rv != 0)
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break;
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sc->sc_rpos += amnt;
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} else {
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break;
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}
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}
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return rv;
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}
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static int
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powermac_nvram_write(struct cdev *dev, struct uio *uio, int ioflag)
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{
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int rv, amnt, data_available;
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struct powermac_nvram_softc *sc;
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sc = NVRAM_SOFTC(NVRAM_UNIT(dev));
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if (sc->sc_wpos >= sizeof(sc->sc_data))
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return EINVAL;
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rv = 0;
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while (uio->uio_resid > 0) {
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data_available = sizeof(sc->sc_data) - sc->sc_wpos;
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if (data_available > 0) {
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amnt = MIN(uio->uio_resid, data_available);
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rv = uiomove((void *)(sc->sc_data + sc->sc_wpos),
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amnt, uio);
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if (rv != 0)
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break;
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sc->sc_wpos += amnt;
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} else {
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break;
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}
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}
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return rv;
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}
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static int
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powermac_nvram_check(void *data)
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{
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struct core99_header *header;
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header = (struct core99_header *)data;
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if (header->chrp_header.signature != CORE99_SIGNATURE)
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return -1;
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if (header->chrp_header.chrp_checksum !=
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chrp_checksum(header->chrp_header.signature,
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(uint8_t *)&(header->chrp_header.length),
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(uint8_t *)&(header->adler_checksum)))
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return -1;
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if (header->adler_checksum !=
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adler_checksum((uint8_t *)&(header->generation),
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NVRAM_SIZE - offsetof(struct core99_header, generation)))
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return -1;
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return header->generation;
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}
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static int
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chrp_checksum(int sum, uint8_t *data, uint8_t *end)
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{
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for (; data < end; data++)
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sum += data[0];
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while (sum > 0xff)
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sum = (sum & 0xff) + (sum >> 8);
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return sum;
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}
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static uint32_t
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adler_checksum(uint8_t *data, int len)
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{
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uint32_t low, high;
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int i;
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low = 1;
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high = 0;
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for (i = 0; i < len; i++) {
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if ((i % 5000) == 0) {
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high %= 65521UL;
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high %= 65521UL;
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}
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low += data[i];
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high += low;
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}
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low %= 65521UL;
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high %= 65521UL;
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return (high << 16) | low;
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}
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#define OUTB_DELAY(a, v) outb(a, v); DELAY(1);
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static int
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wait_operation_complete(uint8_t *bank)
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{
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int i;
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for (i = 1000000; i != 0; i--)
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if ((inb(bank) ^ inb(bank)) == 0)
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return 0;
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return -1;
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}
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static int
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erase_bank(device_t dev, uint8_t *bank)
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{
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unsigned int i;
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/* Unlock 1 */
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OUTB_DELAY(bank + 0x555, 0xaa);
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/* Unlock 2 */
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OUTB_DELAY(bank + 0x2aa, 0x55);
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/* Sector-Erase */
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OUTB_DELAY(bank + 0x555, 0x80);
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OUTB_DELAY(bank + 0x555, 0xaa);
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OUTB_DELAY(bank + 0x2aa, 0x55);
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OUTB_DELAY(bank, 0x30);
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if (wait_operation_complete(bank) != 0) {
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device_printf(dev, "flash erase timeout\n");
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return -1;
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}
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/* Reset */
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OUTB_DELAY(bank, 0xf0);
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for (i = 0; i < NVRAM_SIZE; i++) {
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if (bank[i] != 0xff) {
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device_printf(dev, "flash erase has failed\n");
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return -1;
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}
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}
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return 0;
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}
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static int
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write_bank(device_t dev, uint8_t *bank, uint8_t *data)
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{
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unsigned int i;
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for (i = 0; i < NVRAM_SIZE; i++) {
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/* Unlock 1 */
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OUTB_DELAY(bank + 0x555, 0xaa);
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/* Unlock 2 */
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OUTB_DELAY(bank + 0x2aa, 0x55);
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/* Write single word */
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OUTB_DELAY(bank + 0x555, 0xa0);
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OUTB_DELAY(bank + i, data[i]);
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if (wait_operation_complete(bank) != 0) {
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device_printf(dev, "flash write timeout\n");
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return -1;
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}
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}
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/* Reset */
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OUTB_DELAY(bank, 0xf0);
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for (i = 0; i < NVRAM_SIZE; i++) {
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if (bank[i] != data[i]) {
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device_printf(dev, "flash write has failed\n");
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return -1;
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}
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}
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return 0;
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}
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