784a797eed
The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
575 lines
14 KiB
C
575 lines
14 KiB
C
/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/types.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/rman.h>
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#include <sys/pciio.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pci_private.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/md_var.h>
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#include <machine/intr_machdep.h>
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#include <machine/cpuregs.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/interrupt.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/pic.h>
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#include <mips/nlm/hal/bridge.h>
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#include <mips/nlm/hal/gbu.h>
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#include <mips/nlm/hal/pcibus.h>
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#include <mips/nlm/hal/uart.h>
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#include <mips/nlm/xlp.h>
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#include "pcib_if.h"
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#include "pci_if.h"
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static int
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xlp_pci_attach(device_t dev)
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{
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struct pci_devinfo *dinfo;
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device_t pcib;
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int maxslots, s, f, pcifunchigh, irq;
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int busno, node, devoffset;
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uint16_t devid;
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uint8_t hdrtype;
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/*
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* The on-chip devices are on a bus that is almost, but not
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* quite, completely like PCI. Add those things by hand.
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*/
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pcib = device_get_parent(dev);
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busno = pcib_get_bus(dev);
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maxslots = PCIB_MAXSLOTS(pcib);
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for (s = 0; s <= maxslots; s++) {
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pcifunchigh = 0;
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f = 0;
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hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1);
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if (hdrtype & PCIM_MFDEV)
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pcifunchigh = PCI_FUNCMAX;
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node = s / 8;
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for (f = 0; f <= pcifunchigh; f++) {
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devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f);
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if (!nlm_dev_exists(devoffset))
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continue;
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/* Find if there is a desc for the SoC device */
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devid = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_DEVICE, 2);
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/* Skip devices that don't have a proper PCI header */
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switch (devid) {
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case PCI_DEVICE_ID_NLM_ICI:
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case PCI_DEVICE_ID_NLM_PIC:
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case PCI_DEVICE_ID_NLM_FMN:
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case PCI_DEVICE_ID_NLM_UART:
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case PCI_DEVICE_ID_NLM_I2C:
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case PCI_DEVICE_ID_NLM_NOR:
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case PCI_DEVICE_ID_NLM_MMC:
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continue;
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case PCI_DEVICE_ID_NLM_EHCI:
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irq = PIC_USB_IRQ(f);
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PCIB_WRITE_CONFIG(pcib, busno, s, f,
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XLP_PCI_DEVSCRATCH_REG0 << 2,
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(1 << 8) | irq, 4);
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}
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dinfo = pci_read_device(pcib, dev, pcib_get_domain(dev),
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busno, s, f);
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pci_add_child(dev, dinfo);
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}
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}
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return (bus_generic_attach(dev));
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}
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static int
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xlp_pci_probe(device_t dev)
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{
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device_t pcib;
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pcib = device_get_parent(dev);
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/*
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* Only the top level bus has SoC devices, leave the rest to
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* Generic PCI code
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*/
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if (strcmp(device_get_nameunit(pcib), "pcib0") != 0)
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return (ENXIO);
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device_set_desc(dev, "XLP SoCbus");
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return (BUS_PROBE_DEFAULT);
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}
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static devclass_t pci_devclass;
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static device_method_t xlp_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, xlp_pci_probe),
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DEVMETHOD(device_attach, xlp_pci_attach),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc),
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pci_driver);
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DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0);
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static int
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xlp_pcib_probe(device_t dev)
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{
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if (ofw_bus_is_compatible(dev, "netlogic,xlp-pci")) {
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device_set_desc(dev, "XLP PCI bus");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0;
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return (0);
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case PCIB_IVAR_BUS:
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*result = 0;
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return (0);
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}
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return (ENOENT);
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}
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static int
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xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
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{
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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return (EINVAL);
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case PCIB_IVAR_BUS:
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return (EINVAL);
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}
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return (ENOENT);
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}
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static int
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xlp_pcib_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static u_int32_t
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xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, int width)
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{
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uint32_t data = 0;
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uint64_t cfgaddr;
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int regindex = reg/sizeof(uint32_t);
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cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
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if ((width == 2) && (reg & 1))
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return 0xFFFFFFFF;
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else if ((width == 4) && (reg & 3))
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return 0xFFFFFFFF;
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/*
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* The intline and int pin of SoC devices are DOA, except
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* for bridges (slot %8 == 1).
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* use the values we stashed in a writable PCI scratch reg.
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*/
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if (b == 0 && regindex == 0xf && s % 8 > 1)
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regindex = XLP_PCI_DEVSCRATCH_REG0;
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data = nlm_read_pci_reg(cfgaddr, regindex);
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if (width == 1)
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return ((data >> ((reg & 3) << 3)) & 0xff);
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else if (width == 2)
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return ((data >> ((reg & 3) << 3)) & 0xffff);
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else
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return (data);
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}
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static void
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xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, u_int32_t val, int width)
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{
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uint64_t cfgaddr;
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uint32_t data = 0;
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int regindex = reg / sizeof(uint32_t);
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cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
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if ((width == 2) && (reg & 1))
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return;
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else if ((width == 4) && (reg & 3))
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return;
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if (width == 1) {
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data = nlm_read_pci_reg(cfgaddr, regindex);
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data = (data & ~(0xff << ((reg & 3) << 3))) |
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(val << ((reg & 3) << 3));
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} else if (width == 2) {
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data = nlm_read_pci_reg(cfgaddr, regindex);
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data = (data & ~(0xffff << ((reg & 3) << 3))) |
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(val << ((reg & 3) << 3));
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} else {
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data = val;
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}
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/*
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* use shadow reg for intpin/intline which are dead
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*/
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if (b == 0 && regindex == 0xf && s % 8 > 1)
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regindex = XLP_PCI_DEVSCRATCH_REG0;
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nlm_write_pci_reg(cfgaddr, regindex, data);
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}
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/*
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* Enable byte swap in hardware when compiled big-endian.
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* Programs a link's PCIe SWAP regions from the link's IO and MEM address
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* ranges.
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*/
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static void
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xlp_pcib_hardware_swap_enable(int node, int link)
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{
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#if BYTE_ORDER == BIG_ENDIAN
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uint64_t bbase, linkpcibase;
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uint32_t bar;
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int pcieoffset;
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pcieoffset = XLP_IO_PCIE_OFFSET(node, link);
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if (!nlm_dev_exists(pcieoffset))
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return;
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bbase = nlm_get_bridge_regbase(node);
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linkpcibase = nlm_pcicfg_base(pcieoffset);
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bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link);
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nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar);
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bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link);
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nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF);
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bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link);
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nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar);
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bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
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nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
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#endif
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}
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static int
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xlp_pcib_attach(device_t dev)
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{
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int node, link;
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/* enable hardware swap on all nodes/links */
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for (node = 0; node < XLP_MAX_NODES; node++)
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for (link = 0; link < 4; link++)
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xlp_pcib_hardware_swap_enable(node, link);
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device_add_child(dev, "pci", -1);
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bus_generic_attach(dev);
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return (0);
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}
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/*
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* XLS PCIe can have upto 4 links, and each link has its on IRQ
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* Find the link on which the device is on
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*/
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static int
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xlp_pcie_link(device_t pcib, device_t dev)
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{
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device_t parent, tmp;
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/* find the lane on which the slot is connected to */
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tmp = dev;
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while (1) {
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parent = device_get_parent(tmp);
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if (parent == NULL || parent == pcib) {
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device_printf(dev, "Cannot find parent bus\n");
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return (-1);
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}
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if (strcmp(device_get_nameunit(parent), "pci0") == 0)
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break;
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tmp = parent;
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}
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return (pci_get_function(tmp));
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}
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static int
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xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
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{
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int i, link;
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/*
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* Each link has 32 MSIs that can be allocated, but for now
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* we only support one device per link.
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* msi_alloc() equivalent is needed when we start supporting
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* bridges on the PCIe link.
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*/
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link = xlp_pcie_link(pcib, dev);
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if (link == -1)
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return (ENXIO);
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/*
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* encode the irq so that we know it is a MSI interrupt when we
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* setup interrupts
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*/
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for (i = 0; i < count; i++)
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irqs[i] = 64 + link * 32 + i;
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return (0);
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}
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static int
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xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs)
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{
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return (0);
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}
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static int
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xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
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uint32_t *data)
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{
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int link;
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if (irq < 64) {
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device_printf(dev, "%s: map_msi for irq %d - ignored",
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device_get_nameunit(pcib), irq);
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return (ENXIO);
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}
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link = (irq - 64) / 32;
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*addr = MIPS_MSI_ADDR(0);
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*data = MIPS_MSI_DATA(PIC_PCIE_IRQ(link));
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return (0);
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}
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static void
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bridge_pcie_ack(int irq, void *arg)
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{
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uint32_t node,reg;
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uint64_t base;
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node = nlm_nodeid();
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reg = PCIE_MSI_STATUS;
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switch (irq) {
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case PIC_PCIE_0_IRQ:
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base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node));
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break;
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case PIC_PCIE_1_IRQ:
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base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node));
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break;
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case PIC_PCIE_2_IRQ:
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base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node));
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break;
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case PIC_PCIE_3_IRQ:
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base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node));
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break;
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default:
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return;
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}
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nlm_write_pci_reg(base, reg, 0xFFFFFFFF);
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return;
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}
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static int
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mips_platform_pcib_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags, driver_filter_t *filt,
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driver_intr_t *intr, void *arg, void **cookiep)
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{
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int error = 0;
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int xlpirq;
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error = rman_activate_resource(irq);
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if (error)
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return error;
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if (rman_get_start(irq) != rman_get_end(irq)) {
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device_printf(dev, "Interrupt allocation %ju != %ju\n",
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rman_get_start(irq), rman_get_end(irq));
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return (EINVAL);
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}
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xlpirq = rman_get_start(irq);
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if (xlpirq == 0)
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return (0);
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if (strcmp(device_get_name(dev), "pcib") != 0)
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return (0);
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/*
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* temporary hack for MSI, we support just one device per
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* link, and assign the link interrupt to the device interrupt
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*/
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if (xlpirq >= 64) {
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int node, val, link;
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uint64_t base;
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xlpirq -= 64;
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if (xlpirq % 32 != 0)
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return (0);
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node = nlm_nodeid();
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link = xlpirq / 32;
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base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link));
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/* MSI Interrupt Vector enable at bridge's configuration */
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nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN);
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val = nlm_read_pci_reg(base, PCIE_INT_EN0);
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/* MSI Interrupt enable at bridge's configuration */
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nlm_write_pci_reg(base, PCIE_INT_EN0,
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(val | PCIE_MSI_INT_EN));
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/* legacy interrupt disable at bridge */
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val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD);
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nlm_write_pci_reg(base, PCIE_BRIDGE_CMD,
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(val | PCIM_CMD_INTxDIS));
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/* MSI address update at bridge */
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nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL,
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MSI_MIPS_ADDR_BASE);
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nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0);
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val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP);
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/* MSI capability enable at bridge */
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nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP,
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(val | (PCIM_MSICTRL_MSI_ENABLE << 16) |
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(PCIM_MSICTRL_MMC_32 << 16)));
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xlpirq = PIC_PCIE_IRQ(link);
|
|
}
|
|
|
|
/* if it is for real PCIe, we need to ack at bridge too */
|
|
if (xlpirq >= PIC_PCIE_IRQ(0) && xlpirq <= PIC_PCIE_IRQ(3))
|
|
xlp_set_bus_ack(xlpirq, bridge_pcie_ack, NULL);
|
|
cpu_establish_hardintr(device_get_name(child), filt, intr, arg,
|
|
xlpirq, flags, cookiep);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
mips_platform_pcib_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie)
|
|
{
|
|
if (strcmp(device_get_name(child), "pci") == 0) {
|
|
/* if needed reprogram the pic to clear pcix related entry */
|
|
device_printf(dev, "teardown intr\n");
|
|
}
|
|
return (bus_generic_teardown_intr(dev, child, irq, cookie));
|
|
}
|
|
|
|
static int
|
|
mips_pcib_route_interrupt(device_t bus, device_t dev, int pin)
|
|
{
|
|
int f, d;
|
|
|
|
/*
|
|
* Validate requested pin number.
|
|
*/
|
|
if ((pin < 1) || (pin > 4))
|
|
return (255);
|
|
|
|
if (pci_get_bus(dev) == 0 &&
|
|
pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) {
|
|
f = pci_get_function(dev);
|
|
d = pci_get_slot(dev) % 8;
|
|
|
|
/*
|
|
* For PCIe links, return link IRT, for other SoC devices
|
|
* get the IRT from its PCIe header
|
|
*/
|
|
if (d == 1)
|
|
return (PIC_PCIE_IRQ(f));
|
|
else
|
|
return (255); /* use intline, don't reroute */
|
|
} else {
|
|
/* Regular PCI devices */
|
|
return (PIC_PCIE_IRQ(xlp_pcie_link(bus, dev)));
|
|
}
|
|
}
|
|
|
|
static device_method_t xlp_pcib_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, xlp_pcib_probe),
|
|
DEVMETHOD(device_attach, xlp_pcib_attach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots),
|
|
DEVMETHOD(pcib_read_config, xlp_pcib_read_config),
|
|
DEVMETHOD(pcib_write_config, xlp_pcib_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt),
|
|
|
|
DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi),
|
|
DEVMETHOD(pcib_release_msi, xlp_release_msi),
|
|
DEVMETHOD(pcib_map_msi, xlp_map_msi),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t xlp_pcib_driver = {
|
|
"pcib",
|
|
xlp_pcib_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t pcib_devclass;
|
|
DRIVER_MODULE(xlp_pcib, simplebus, xlp_pcib_driver, pcib_devclass, 0, 0);
|