130 lines
4.1 KiB
C
130 lines
4.1 KiB
C
/*
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* Copyright (c) 2005 Topspin Communications. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef INFINIBAND_ARCH_H
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#define INFINIBAND_ARCH_H
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#include <stdint.h>
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#include <infiniband/endian.h>
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#include <infiniband/byteswap.h>
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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static inline uint64_t htonll(uint64_t x) { return bswap_64(x); }
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static inline uint64_t ntohll(uint64_t x) { return bswap_64(x); }
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#elif __BYTE_ORDER == __BIG_ENDIAN
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static inline uint64_t htonll(uint64_t x) { return x; }
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static inline uint64_t ntohll(uint64_t x) { return x; }
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#else
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#error __BYTE_ORDER is neither __LITTLE_ENDIAN nor __BIG_ENDIAN
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#endif
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/*
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* Architecture-specific defines. Currently, an architecture is
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* required to implement the following operations:
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*
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* mb() - memory barrier. No loads or stores may be reordered across
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* this macro by either the compiler or the CPU.
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* rmb() - read memory barrier. No loads may be reordered across this
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* macro by either the compiler or the CPU.
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* wmb() - write memory barrier. No stores may be reordered across
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* this macro by either the compiler or the CPU.
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* wc_wmb() - flush write combine buffers. No write-combined writes
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* will be reordered across this macro by either the compiler or
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* the CPU.
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*/
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#if defined(__i386__)
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#define mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
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#define rmb() mb()
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#define wmb() asm volatile("" ::: "memory")
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#define wc_wmb() mb()
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#elif defined(__x86_64__)
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/*
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* Only use lfence for mb() and rmb() because we don't care about
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* ordering against non-temporal stores (for now at least).
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*/
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#define mb() asm volatile("lfence" ::: "memory")
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#define rmb() mb()
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#define wmb() asm volatile("" ::: "memory")
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#define wc_wmb() asm volatile("sfence" ::: "memory")
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#elif defined(__PPC64__)
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#define mb() asm volatile("sync" ::: "memory")
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#define rmb() asm volatile("lwsync" ::: "memory")
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#define wmb() mb()
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#define wc_wmb() wmb()
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#elif defined(__ia64__)
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#define mb() asm volatile("mf" ::: "memory")
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#define rmb() mb()
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#define wmb() mb()
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#define wc_wmb() asm volatile("fwb" ::: "memory")
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#elif defined(__PPC__)
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#define mb() asm volatile("sync" ::: "memory")
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#define rmb() mb()
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#define wmb() mb()
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#define wc_wmb() wmb()
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#elif defined(__sparc_v9__)
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#define mb() asm volatile("membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad" ::: "memory")
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#define rmb() asm volatile("membar #LoadLoad" ::: "memory")
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#define wmb() asm volatile("membar #StoreStore" ::: "memory")
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#define wc_wmb() wmb()
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#elif defined(__sparc__)
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#define mb() asm volatile("" ::: "memory")
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#define rmb() mb()
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#define wmb() mb()
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#define wc_wmb() wmb()
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#else
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#warning No architecture specific defines found. Using generic implementation.
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#define mb() asm volatile("" ::: "memory")
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#define rmb() mb()
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#define wmb() mb()
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#define wc_wmb() wmb()
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#endif
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#endif /* INFINIBAND_ARCH_H */
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