e5acd89c78
This is only the minimum set of files needed to boot in qemu. As such it is missing a few things. The bus_dma code is currently only stub functions with a full implementation from the development tree to follow. The gic driver has been copied as the interrupt framework is different. It is expected the two drivers will be merged by the arm intrng project, however this will need to be imported into the tree and support for arm64 would need to be added. This includes code developed by myself, SemiHalf, Ed Maste, and Robin Randhawa from ARM. This has been funded by the FreeBSD Foundation, with early development by myself in my spare time with assistance from Robin. Differential Revision: https://reviews.freebsd.org/D2199 Reviewed by: emaste, imp Relnotes: yes Sponsored by: The FreeBSD Foundation
86 lines
2.9 KiB
C
86 lines
2.9 KiB
C
/*-
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* Copyright (c) 2013, 2014 Andrew Turner
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_HYPERVISOR_H_
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#define _MACHINE_HYPERVISOR_H_
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/*
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* These registers are only useful when in hypervisor context,
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* e.g. specific to EL2, or controlling the hypervisor.
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*/
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/*
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* Architecture feature trap register
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*/
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#define CPTR_RES0 0x7fefc800
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#define CPTR_RES1 0x000033ff
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#define CPTR_TFP 0x00000400
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#define CPTR_TTA 0x00100000
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#define CPTR_TCPAC 0x80000000
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/*
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* Hypervisor Config Register
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*/
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#define HCR_VM 0x0000000000000001
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#define HCR_SWIO 0x0000000000000002
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#define HCR_PTW 0x0000000000000004
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#define HCR_FMO 0x0000000000000008
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#define HCR_IMO 0x0000000000000010
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#define HCR_AMO 0x0000000000000020
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#define HCR_VF 0x0000000000000040
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#define HCR_VI 0x0000000000000080
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#define HCR_VSE 0x0000000000000100
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#define HCR_FB 0x0000000000000200
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#define HCR_BSU_MASK 0x0000000000000c00
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#define HCR_DC 0x0000000000001000
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#define HCR_TWI 0x0000000000002000
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#define HCR_TWE 0x0000000000004000
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#define HCR_TID0 0x0000000000008000
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#define HCR_TID1 0x0000000000010000
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#define HCR_TID2 0x0000000000020000
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#define HCR_TID3 0x0000000000040000
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#define HCR_TSC 0x0000000000080000
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#define HCR_TIDCP 0x0000000000100000
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#define HCR_TACR 0x0000000000200000
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#define HCR_TSW 0x0000000000400000
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#define HCR_TPC 0x0000000000800000
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#define HCR_TPU 0x0000000001000000
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#define HCR_TTLB 0x0000000002000000
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#define HCR_TVM 0x0000000004000000
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#define HCR_TGE 0x0000000008000000
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#define HCR_TDZ 0x0000000010000000
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#define HCR_HCD 0x0000000020000000
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#define HCR_TRVM 0x0000000040000000
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#define HCR_RW 0x0000000080000000
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#define HCR_CD 0x0000000100000000
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#define HCR_ID 0x0000000200000000
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#endif
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