7910492ee4
These are needed for some particular port configurations where the default speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit PLL rate requires a similar MII clock rate, rather than a fixed MII rate.) This is: * only currently implemented for the ar71xx; * isn't used anywhere (yet), as the final interface for this hasn't yet been determined. |
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adm5120 | ||
alchemy | ||
atheros | ||
cavium | ||
compile | ||
conf | ||
idt | ||
include | ||
malta | ||
mips | ||
nlm | ||
rmi | ||
rt305x | ||
sentry5 | ||
sibyte |