fd20cedd09
Create new driver which initializes Arndale PHY and calls ehci_init Reviewed by: hselasky Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: Juniper Networks Inc. Differential Revision: https://reviews.freebsd.org/D4192
416 lines
11 KiB
C
416 lines
11 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Samsung Exynos 5 Interrupt Combiner
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* Chapter 7, Exynos 5 Dual User's Manual Public Rev 1.00
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*/
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#ifdef USB_GLOBAL_INCLUDE_FILE
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#include USB_GLOBAL_INCLUDE_FILE
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#else
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#endif
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#include <arm/samsung/exynos/exynos5_common.h>
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#include <arm/samsung/exynos/exynos5_combiner.h>
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#define NGRP 32
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#define IESR(n) (0x10 * n + 0x0) /* Interrupt enable set */
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#define IECR(n) (0x10 * n + 0x4) /* Interrupt enable clear */
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#define ISTR(n) (0x10 * n + 0x8) /* Interrupt status */
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#define IMSR(n) (0x10 * n + 0xC) /* Interrupt masked status */
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#define CIPSR 0x100 /* Combined interrupt pending */
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struct combiner_softc {
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struct resource *res[1 + NGRP];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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void *ih[NGRP];
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device_t dev;
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};
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struct combiner_softc *combiner_sc;
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static struct resource_spec combiner_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ SYS_RES_IRQ, 3, RF_ACTIVE },
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{ SYS_RES_IRQ, 4, RF_ACTIVE },
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{ SYS_RES_IRQ, 5, RF_ACTIVE },
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{ SYS_RES_IRQ, 6, RF_ACTIVE },
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{ SYS_RES_IRQ, 7, RF_ACTIVE },
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{ SYS_RES_IRQ, 8, RF_ACTIVE },
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{ SYS_RES_IRQ, 9, RF_ACTIVE },
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{ SYS_RES_IRQ, 10, RF_ACTIVE },
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{ SYS_RES_IRQ, 11, RF_ACTIVE },
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{ SYS_RES_IRQ, 12, RF_ACTIVE },
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{ SYS_RES_IRQ, 13, RF_ACTIVE },
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{ SYS_RES_IRQ, 14, RF_ACTIVE },
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{ SYS_RES_IRQ, 15, RF_ACTIVE },
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{ SYS_RES_IRQ, 16, RF_ACTIVE },
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{ SYS_RES_IRQ, 17, RF_ACTIVE },
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{ SYS_RES_IRQ, 18, RF_ACTIVE },
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{ SYS_RES_IRQ, 19, RF_ACTIVE },
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{ SYS_RES_IRQ, 20, RF_ACTIVE },
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{ SYS_RES_IRQ, 21, RF_ACTIVE },
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{ SYS_RES_IRQ, 22, RF_ACTIVE },
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{ SYS_RES_IRQ, 23, RF_ACTIVE },
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{ SYS_RES_IRQ, 24, RF_ACTIVE },
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{ SYS_RES_IRQ, 25, RF_ACTIVE },
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{ SYS_RES_IRQ, 26, RF_ACTIVE },
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{ SYS_RES_IRQ, 27, RF_ACTIVE },
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{ SYS_RES_IRQ, 28, RF_ACTIVE },
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{ SYS_RES_IRQ, 29, RF_ACTIVE },
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{ SYS_RES_IRQ, 30, RF_ACTIVE },
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{ SYS_RES_IRQ, 31, RF_ACTIVE },
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{ -1, 0 }
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};
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struct combiner_entry {
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int combiner_id;
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int bit;
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char *source_name;
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};
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static struct combiner_entry interrupt_table[] = {
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{ 63, 1, "EINT[15]" },
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{ 63, 0, "EINT[14]" },
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{ 62, 1, "EINT[13]" },
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{ 62, 0, "EINT[12]" },
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{ 61, 1, "EINT[11]" },
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{ 61, 0, "EINT[10]" },
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{ 60, 1, "EINT[9]" },
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{ 60, 0, "EINT[8]" },
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{ 59, 1, "EINT[7]" },
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{ 59, 0, "EINT[6]" },
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{ 58, 1, "EINT[5]" },
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{ 58, 0, "EINT[4]" },
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{ 57, 3, "MCT_G3" },
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{ 57, 2, "MCT_G2" },
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{ 57, 1, "EINT[3]" },
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{ 57, 0, "EINT[2]" },
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{ 56, 6, "SYSMMU_G2D[1]" },
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{ 56, 5, "SYSMMU_G2D[0]" },
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{ 56, 2, "SYSMMU_FIMC_LITE1[1]" },
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{ 56, 1, "SYSMMU_FIMC_LITE1[0]" },
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{ 56, 0, "EINT[1]" },
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{ 55, 4, "MCT_G1" },
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{ 55, 3, "MCT_G0" },
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{ 55, 0, "EINT[0]" },
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{ 54, 7, "CPU_nCNTVIRQ[1]" },
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{ 54, 6, "CPU_nCTIIRQ[1]" },
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{ 54, 5, "CPU_nCNTPSIRQ[1]" },
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{ 54, 4, "CPU_nPMUIRQ[1]" },
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{ 54, 3, "CPU_nCNTPNSIRQ[1]" },
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{ 54, 2, "CPU_PARITYFAILSCU[1]" },
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{ 54, 1, "CPU_nCNTHPIRQ[1]" },
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{ 54, 0, "PARITYFAIL[1]" },
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{ 53, 1, "CPU_nIRQ[1]" },
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{ 52, 0, "CPU_nIRQ[0]" },
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{ 51, 7, "CPU_nRAMERRIRQ" },
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{ 51, 6, "CPU_nAXIERRIRQ" },
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{ 51, 4, "INT_COMB_ISP_GIC" },
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{ 51, 3, "INT_COMB_IOP_GIC" },
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{ 51, 2, "CCI_nERRORIRQ" },
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{ 51, 1, "INT_COMB_ARMISP_GIC" },
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{ 51, 0, "INT_COMB_ARMIOP_GIC" },
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{ 50, 7, "DISP1[3]" },
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{ 50, 6, "DISP1[2]" },
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{ 50, 5, "DISP1[1]" },
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{ 50, 4, "DISP1[0]" },
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{ 49, 3, "SSCM_PULSE_IRQ_C2CIF[1]" },
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{ 49, 2, "SSCM_PULSE_IRQ_C2CIF[0]" },
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{ 49, 1, "SSCM_IRQ_C2CIF[1]" },
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{ 49, 0, "SSCM_IRQ_C2CIF[0]" },
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{ 48, 3, "PEREV_M1_CDREX" },
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{ 48, 2, "PEREV_M0_CDREX" },
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{ 48, 1, "PEREV_A1_CDREX" },
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{ 48, 0, "PEREV_A0_CDREX" },
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{ 47, 3, "MDMA0_ABORT" },
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/* 46 is fully reserved */
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{ 45, 1, "MDMA1_ABORT" },
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/* 44 is fully reserved */
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{ 43, 7, "SYSMMU_DRCISP[1]" },
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{ 43, 6, "SYSMMU_DRCISP[0]" },
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{ 43, 1, "SYSMMU_ODC[1]" },
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{ 43, 0, "SYSMMU_ODC[0]" },
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{ 42, 7, "SYSMMU_ISP[1]" },
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{ 42, 6, "SYSMMU_ISP[0]" },
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{ 42, 5, "SYSMMU_DIS0[1]" },
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{ 42, 4, "SYSMMU_DIS0[0]" },
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{ 42, 3, "DP1" },
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{ 41, 5, "SYSMMU_DIS1[1]" },
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{ 41, 4, "SYSMMU_DIS1[0]" },
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{ 40, 6, "SYSMMU_MFCL[1]" },
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{ 40, 5, "SYSMMU_MFCL[0]" },
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{ 39, 5, "SYSMMU_TV_M0[1]" },
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{ 39, 4, "SYSMMU_TV_M0[0]" },
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{ 39, 3, "SYSMMU_MDMA1[1]" },
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{ 39, 2, "SYSMMU_MDMA1[0]" },
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{ 39, 1, "SYSMMU_MDMA0[1]" },
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{ 39, 0, "SYSMMU_MDMA0[0]" },
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{ 38, 7, "SYSMMU_SSS[1]" },
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{ 38, 6, "SYSMMU_SSS[0]" },
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{ 38, 5, "SYSMMU_RTIC[1]" },
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{ 38, 4, "SYSMMU_RTIC[0]" },
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{ 38, 3, "SYSMMU_MFCR[1]" },
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{ 38, 2, "SYSMMU_MFCR[0]" },
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{ 38, 1, "SYSMMU_ARM[1]" },
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{ 38, 0, "SYSMMU_ARM[0]" },
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{ 37, 7, "SYSMMU_3DNR[1]" },
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{ 37, 6, "SYSMMU_3DNR[0]" },
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{ 37, 5, "SYSMMU_MCUISP[1]" },
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{ 37, 4, "SYSMMU_MCUISP[0]" },
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{ 37, 3, "SYSMMU_SCALERCISP[1]" },
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{ 37, 2, "SYSMMU_SCALERCISP[0]" },
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{ 37, 1, "SYSMMU_FDISP[1]" },
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{ 37, 0, "SYSMMU_FDISP[0]" },
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{ 36, 7, "MCUIOP_CTIIRQ" },
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{ 36, 6, "MCUIOP_PMUIRQ" },
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{ 36, 5, "MCUISP_CTIIRQ" },
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{ 36, 4, "MCUISP_PMUIRQ" },
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{ 36, 3, "SYSMMU_JPEGX[1]" },
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{ 36, 2, "SYSMMU_JPEGX[0]" },
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{ 36, 1, "SYSMMU_ROTATOR[1]" },
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{ 36, 0, "SYSMMU_ROTATOR[0]" },
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{ 35, 7, "SYSMMU_SCALERPISP[1]" },
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{ 35, 6, "SYSMMU_SCALERPISP[0]" },
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{ 35, 5, "SYSMMU_FIMC_LITE0[1]" },
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{ 35, 4, "SYSMMU_FIMC_LITE0[0]" },
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{ 35, 3, "SYSMMU_DISP1_M0[1]" },
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{ 35, 2, "SYSMMU_DISP1_M0[0]" },
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{ 35, 1, "SYSMMU_FIMC_LITE2[1]" },
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{ 35, 0, "SYSMMU_FIMC_LITE2[0]" },
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{ 34, 7, "SYSMMU_GSCL3[1]" },
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{ 34, 6, "SYSMMU_GSCL3[0]" },
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{ 34, 5, "SYSMMU_GSCL2[1]" },
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{ 34, 4, "SYSMMU_GSCL2[0]" },
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{ 34, 3, "SYSMMU_GSCL1[1]" },
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{ 34, 2, "SYSMMU_GSCL1[0]" },
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{ 34, 1, "SYSMMU_GSCL0[1]" },
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{ 34, 0, "SYSMMU_GSCL0[0]" },
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{ 33, 7, "CPU_nCNTVIRQ[0]" },
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{ 33, 6, "CPU_nCNTPSIRQ[0]" },
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{ 33, 5, "CPU_nCNTPSNIRQ[0]" },
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{ 33, 4, "CPU_nCNTHPIRQ[0]" },
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{ 33, 3, "CPU_nCTIIRQ[0]" },
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{ 33, 2, "CPU_nPMUIRQ[0]" },
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{ 33, 1, "CPU_PARITYFAILSCU[0]" },
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{ 33, 0, "CPU_PARITYFAIL0" },
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{ 32, 7, "TZASC_XR1BXW" },
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{ 32, 6, "TZASC_XR1BXR" },
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{ 32, 5, "TZASC_XLBXW" },
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{ 32, 4, "TZASC_XLBXR" },
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{ 32, 3, "TZASC_DRBXW" },
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{ 32, 2, "TZASC_DRBXR" },
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{ 32, 1, "TZASC_CBXW" },
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{ 32, 0, "TZASC_CBXR" },
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{ -1, -1, NULL },
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};
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struct combined_intr {
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uint32_t enabled;
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void (*ih) (void *);
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void *ih_user;
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};
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static struct combined_intr intr_map[32][8];
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static void
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combiner_intr(void *arg)
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{
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struct combiner_softc *sc;
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void (*ih) (void *);
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void *ih_user;
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int enabled;
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int intrs;
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int shift;
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int cirq;
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int grp;
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int i,n;
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sc = arg;
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intrs = READ4(sc, CIPSR);
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for (grp = 0; grp < 32; grp++) {
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if (intrs & (1 << grp)) {
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n = (grp / 4);
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shift = (grp % 4) * 8;
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cirq = READ4(sc, ISTR(n));
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for (i = 0; i < 8; i++) {
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if (cirq & (1 << (i + shift))) {
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ih = intr_map[grp][i].ih;
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ih_user = intr_map[grp][i].ih_user;
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enabled = intr_map[grp][i].enabled;
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if (enabled && (ih != NULL)) {
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ih(ih_user);
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}
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}
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}
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}
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}
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}
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void
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combiner_setup_intr(char *source_name, void (*ih)(void *), void *ih_user)
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{
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struct combiner_entry *entry;
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struct combined_intr *cirq;
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struct combiner_softc *sc;
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int shift;
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int reg;
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int grp;
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int n;
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int i;
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sc = combiner_sc;
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if (sc == NULL) {
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device_printf(sc->dev, "Error: combiner is not attached\n");
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return;
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}
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entry = NULL;
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for (i = 0; i < NGRP && interrupt_table[i].bit != -1; i++) {
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if (strcmp(interrupt_table[i].source_name, source_name) == 0) {
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entry = &interrupt_table[i];
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}
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}
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if (entry == NULL) {
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device_printf(sc->dev, "Can't find interrupt name %s\n",
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source_name);
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return;
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}
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#if 0
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device_printf(sc->dev, "Setting up interrupt %s\n", source_name);
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#endif
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grp = entry->combiner_id - 32;
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cirq = &intr_map[grp][entry->bit];
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cirq->enabled = 1;
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cirq->ih = ih;
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cirq->ih_user = ih_user;
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n = grp / 4;
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shift = (grp % 4) * 8 + entry->bit;
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reg = (1 << shift);
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WRITE4(sc, IESR(n), reg);
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}
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static int
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combiner_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "exynos,combiner"))
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return (ENXIO);
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device_set_desc(dev, "Samsung Exynos 5 Interrupt Combiner");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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combiner_attach(device_t dev)
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{
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struct combiner_softc *sc;
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int err;
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int i;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, combiner_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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combiner_sc = sc;
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/* Setup interrupt handler */
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for (i = 0; i < NGRP; i++) {
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err = bus_setup_intr(dev, sc->res[1+i], INTR_TYPE_BIO | \
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INTR_MPSAFE, NULL, combiner_intr, sc, &sc->ih[i]);
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if (err) {
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device_printf(dev, "Unable to alloc int resource.\n");
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return (ENXIO);
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}
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}
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return (0);
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}
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static device_method_t combiner_methods[] = {
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DEVMETHOD(device_probe, combiner_probe),
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DEVMETHOD(device_attach, combiner_attach),
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{ 0, 0 }
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};
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static driver_t combiner_driver = {
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"combiner",
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combiner_methods,
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sizeof(struct combiner_softc),
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};
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static devclass_t combiner_devclass;
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DRIVER_MODULE(combiner, simplebus, combiner_driver, combiner_devclass, 0, 0);
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