239 lines
7.4 KiB
C
239 lines
7.4 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91
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* $FreeBSD$
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*/
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/*
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* NS8250... UART registers.
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*/
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/* 8250 registers #[0-6]. */
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#define com_data 0 /* data register (R/W) */
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#define REG_DATA com_data
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#define com_ier 1 /* interrupt enable register (W) */
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#define REG_IER com_ier
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC"
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#define com_iir 2 /* interrupt identification register (R) */
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#define REG_IIR com_iir
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#define IIR_IMASK 0xf
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#define IIR_RXTOUT 0xc
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#define IIR_BUSY 0x7
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#define IIR_RLS 0x6
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#define IIR_RXRDY 0x4
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#define IIR_TXRDY 0x2
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#define IIR_NOPEND 0x1
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#define IIR_MLSC 0x0
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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#define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY"
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#define com_lcr 3 /* line control register (R/W) */
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#define com_cfcr com_lcr /* character format control register (R/W) */
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#define REG_LCR com_lcr
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#define LCR_DLAB 0x80
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#define CFCR_DLAB LCR_DLAB
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#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
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#define CFCR_EFR_ENABLE LCR_EFR_ENABLE
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#define LCR_SBREAK 0x40
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#define CFCR_SBREAK LCR_SBREAK
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#define LCR_PZERO 0x30
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#define CFCR_PZERO LCR_PZERO
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#define LCR_PONE 0x20
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#define CFCR_PONE LCR_PONE
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#define LCR_PEVEN 0x10
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#define CFCR_PEVEN LCR_PEVEN
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#define LCR_PODD 0x00
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#define CFCR_PODD LCR_PODD
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#define LCR_PENAB 0x08
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#define CFCR_PENAB LCR_PENAB
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#define LCR_STOPB 0x04
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#define CFCR_STOPB LCR_STOPB
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#define LCR_8BITS 0x03
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#define CFCR_8BITS LCR_8BITS
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#define LCR_7BITS 0x02
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#define CFCR_7BITS LCR_7BITS
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#define LCR_6BITS 0x01
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#define CFCR_6BITS LCR_6BITS
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#define LCR_5BITS 0x00
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#define CFCR_5BITS LCR_5BITS
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#define com_mcr 4 /* modem control register (R/W) */
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#define REG_MCR com_mcr
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#define MCR_PRESCALE 0x80 /* only available on 16650 up */
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#define MCR_LOOPBACK 0x10
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#define MCR_IE 0x08
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#define MCR_IENABLE MCR_IE
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#define MCR_DRS 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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#define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE"
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#define com_lsr 5 /* line status register (R/W) */
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#define REG_LSR com_lsr
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#define LSR_RCV_FIFO 0x80
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#define LSR_TEMT 0x40
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#define LSR_TSRE LSR_TEMT
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#define LSR_THRE 0x20
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#define LSR_TXRDY LSR_THRE
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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#define LSR_OE 0x02
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#define LSR_RXRDY 0x01
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#define LSR_RCV_MASK 0x1f
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#define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO"
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#define com_msr 6 /* modem status register (R/W) */
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#define REG_MSR com_msr
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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#define MSR_CTS 0x10
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#define MSR_DDCD 0x08
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#define MSR_TERI 0x04
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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#define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD"
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/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */
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#define com_dll 0 /* divisor latch low (R/W) */
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#define com_dlbl com_dll
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#define com_dlm 1 /* divisor latch high (R/W) */
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#define com_dlbh com_dlm
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#define REG_DLL com_dll
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#define REG_DLH com_dlm
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/* 16450 register #7. Not multiplexed. */
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#define com_scr 7 /* scratch register (R/W) */
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/* 16550 register #2. Not multiplexed. */
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#define com_fcr 2 /* FIFO control register (W) */
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#define com_fifo com_fcr
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#define REG_FCR com_fcr
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#define FCR_ENABLE 0x01
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#define FIFO_ENABLE FCR_ENABLE
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#define FCR_RCV_RST 0x02
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#define FIFO_RCV_RST FCR_RCV_RST
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#define FCR_XMT_RST 0x04
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#define FIFO_XMT_RST FCR_XMT_RST
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#define FCR_DMA 0x08
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#define FIFO_DMA_MODE FCR_DMA
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#define FCR_RX_LOW 0x00
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#define FIFO_RX_LOW FCR_RX_LOW
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#define FCR_RX_MEDL 0x40
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#define FIFO_RX_MEDL FCR_RX_MEDL
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#define FCR_RX_MEDH 0x80
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#define FIFO_RX_MEDH FCR_RX_MEDH
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#define FCR_RX_HIGH 0xc0
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#define FIFO_RX_HIGH FCR_RX_HIGH
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#define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA"
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/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */
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#define com_efr 2 /* enhanced features register (R/W) */
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#define REG_EFR com_efr
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#define EFR_CTS 0x80
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#define EFR_AUTOCTS EFR_CTS
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#define EFR_RTS 0x40
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#define EFR_AUTORTS EFR_RTS
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#define EFR_EFE 0x10 /* enhanced functions enable */
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#define com_xon1 4 /* XON 1 character (R/W) */
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#define com_xon2 5 /* XON 2 character (R/W) */
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#define com_xoff1 6 /* XOFF 1 character (R/W) */
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#define com_xoff2 7 /* XOFF 2 character (R/W) */
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#define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */
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#define REG_USR com_usr
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#define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */
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/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */
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#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */
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/* 16950 register #3. R/W access enabled by ACR[7]. */
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#define com_rfl 3 /* receiver fifo level (R) */
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/*
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* 16950 register #4. Access enabled by ACR[7]. Also requires
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* !LCR_EFR_ENABLE.
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*/
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#define com_tfl 4 /* transmitter fifo level (R) */
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/*
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* 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also
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* requires ACR[6].
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*/
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#define com_icr 5 /* index control register (R/W) */
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/*
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* 16950 register #7. It is the same as com_scr except it has a different
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* abbreviation in the manufacturer's data sheet and it also serves as an
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* index into the Indexed Control register set.
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*/
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#define com_spr com_scr /* scratch pad (and index) register (R/W) */
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#define REG_SPR com_scr
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/*
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* 16950 indexed control registers #[0-0x13]. Access is via index in SPR,
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* data in ICR (if ICR is accessible).
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*/
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#define com_acr 0 /* additional control register (R/W) */
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#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */
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#define ACR_ICRE 0x40 /* ICR enable */
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#define ACR_TLE 0x20 /* TTL/RTL enable */
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#define com_cpr 1 /* clock prescaler register (R/W) */
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#define com_tcr 2 /* times clock register (R/W) */
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#define com_ttl 4 /* transmitter trigger level (R/W) */
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#define com_rtl 5 /* receiver trigger level (R/W) */
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/* ... */
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/* Hardware extension mode register for RSB-2000/3000. */
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#define com_emr com_msr
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#define EMR_EXBUFF 0x04
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#define EMR_CTSFLW 0x08
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#define EMR_DSRFLW 0x10
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#define EMR_RTSFLW 0x20
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#define EMR_DTRFLW 0x40
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#define EMR_EFMODE 0x80
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