86 lines
3.2 KiB
C
86 lines
3.2 KiB
C
/*-
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* Copyright (c) 2010 Adrian Chadd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef __AR91XX_REG_H__
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#define __AR91XX_REG_H__
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#define AR91XX_BASE_FREQ 5000000
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/* reset block */
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#define AR91XX_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c
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#define AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE (1 << 10)
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/* PLL block */
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#define AR91XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
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#define AR91XX_PLL_REG_ETH_CONFIG AR71XX_PLL_CPU_BASE + 0x04
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#define AR91XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14
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#define AR91XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x18
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#define AR91XX_PLL_DIV_SHIFT 0
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#define AR91XX_PLL_DIV_MASK 0x3ff
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#define AR91XX_DDR_DIV_SHIFT 22
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#define AR91XX_DDR_DIV_MASK 0x3
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#define AR91XX_AHB_DIV_SHIFT 19
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#define AR91XX_AHB_DIV_MASK 0x1
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#define AR91XX_ETH0_PLL_SHIFT 20
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#define AR91XX_ETH1_PLL_SHIFT 22
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#define AR91XX_PLL_VAL_1000 0x1a000000
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#define AR91XX_PLL_VAL_100 0x13000a44
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#define AR91XX_PLL_VAL_10 0x00441099
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/* DDR block */
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#define AR91XX_DDR_CTRLBASE (AR71XX_APB_BASE + 0)
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#define AR91XX_DDR_CTRL_SIZE 0x10000
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#define AR91XX_DDR_REG_FLUSH_GE0 AR91XX_DDR_CTRLBASE + 0x7c
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#define AR91XX_DDR_REG_FLUSH_GE1 AR91XX_DDR_CTRLBASE + 0x80
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#define AR91XX_DDR_REG_FLUSH_USB AR91XX_DDR_CTRLBASE + 0x84
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#define AR91XX_DDR_REG_FLUSH_WMAC AR91XX_DDR_CTRLBASE + 0x88
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/* WMAC stuff */
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#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR91XX_WMAC_SIZE 0x30000
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/* GPIO stuff */
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#define AR91XX_GPIO_FUNC_WMAC_LED_EN (1 << 22)
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#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN (1 << 21)
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#define AR91XX_GPIO_FUNC_I2S_REFCLKEN (1 << 20)
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#define AR91XX_GPIO_FUNC_I2S_MCKEN (1 << 19)
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#define AR91XX_GPIO_FUNC_I2S1_EN (1 << 18)
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#define AR91XX_GPIO_FUNC_I2S0_EN (1 << 17)
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#define AR91XX_GPIO_FUNC_SLIC_EN (1 << 16)
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#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN (1 << 9)
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#define AR91XX_GPIO_FUNC_UART_EN (1 << 8)
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#define AR91XX_GPIO_FUNC_USB_CLK_EN (1 << 4)
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#define AR91XX_GPIO_COUNT 22
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#endif
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