7bf9ab5331
The copies of initarm used on platforms with FDT support were almost identical. The differences were pulled out into separate functions that were called by initarm. This change merges the, now identical, copies of initarm and a few of it's support functions. This is a step towards a common kernel on ARMv6.
463 lines
12 KiB
C
463 lines
12 KiB
C
/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
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*/
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#include "opt_ddb.h"
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/frame.h> /* For trapframe_t, used in <machine/machdep.h> */
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#include <machine/machdep.h>
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#include <machine/pmap.h>
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#include <arm/mv/mvreg.h> /* XXX */
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#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */
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#include <arm/mv/mvwin.h>
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#include <dev/fdt/fdt_common.h>
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static int platform_mpp_init(void);
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#define MPP_PIN_MAX 68
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#define MPP_PIN_CELLS 2
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#define MPP_PINS_PER_REG 8
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#define MPP_SEL(pin,func) (((func) & 0xf) << \
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(((pin) % MPP_PINS_PER_REG) * 4))
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static int
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platform_mpp_init(void)
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{
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pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
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int mpp[MPP_PIN_MAX];
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uint32_t ctrl_val, ctrl_offset;
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pcell_t reg[4];
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u_long start, size;
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phandle_t node;
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pcell_t pin_cells, *pinmap_ptr, pin_count;
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ssize_t len;
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int par_addr_cells, par_size_cells;
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int tuple_size, tuples, rv, pins, i, j;
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int mpp_pin, mpp_function;
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/*
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* Try to access the MPP node directly i.e. through /aliases/mpp.
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*/
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if ((node = OF_finddevice("mpp")) != -1)
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if (fdt_is_compatible(node, "mrvl,mpp"))
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goto moveon;
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/*
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* Find the node the long way.
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*/
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if ((node = OF_finddevice("/")) == -1)
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return (ENXIO);
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if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
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return (ENXIO);
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if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
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/*
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* No MPP node. Fall back to how MPP got set by the
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* first-stage loader and try to continue booting.
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*/
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return (0);
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moveon:
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/*
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* Process 'reg' prop.
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*/
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if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
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&par_size_cells)) != 0)
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return(ENXIO);
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tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
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len = OF_getprop(node, "reg", reg, sizeof(reg));
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tuples = len / tuple_size;
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if (tuple_size <= 0)
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return (EINVAL);
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/*
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* Get address/size. XXX we assume only the first 'reg' tuple is used.
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*/
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rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
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&start, &size);
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if (rv != 0)
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return (rv);
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start += fdt_immr_va;
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/*
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* Process 'pin-count' and 'pin-map' props.
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*/
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if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
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return (ENXIO);
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pin_count = fdt32_to_cpu(pin_count);
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if (pin_count > MPP_PIN_MAX)
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return (ERANGE);
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if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
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pin_cells = MPP_PIN_CELLS;
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pin_cells = fdt32_to_cpu(pin_cells);
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if (pin_cells > MPP_PIN_CELLS)
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return (ERANGE);
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tuple_size = sizeof(pcell_t) * pin_cells;
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bzero(pinmap, sizeof(pinmap));
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len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap));
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if (len <= 0)
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return (ERANGE);
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if (len % tuple_size)
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return (ERANGE);
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pins = len / tuple_size;
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if (pins > pin_count)
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return (ERANGE);
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/*
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* Fill out a "mpp[pin] => function" table. All pins unspecified in
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* the 'pin-map' property are defaulted to 0 function i.e. GPIO.
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*/
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bzero(mpp, sizeof(mpp));
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pinmap_ptr = pinmap;
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for (i = 0; i < pins; i++) {
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mpp_pin = fdt32_to_cpu(*pinmap_ptr);
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mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1));
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mpp[mpp_pin] = mpp_function;
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pinmap_ptr += pin_cells;
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}
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/*
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* Prepare and program MPP control register values.
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*/
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ctrl_offset = 0;
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for (i = 0; i < pin_count;) {
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ctrl_val = 0;
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for (j = 0; j < MPP_PINS_PER_REG; j++) {
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if (i + j == pin_count - 1)
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break;
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ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
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}
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i += MPP_PINS_PER_REG;
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bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
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ctrl_val);
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#if defined(SOC_MV_ORION)
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/*
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* Third MPP reg on Orion SoC is placed
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* non-linearly (with different offset).
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*/
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if (i == (2 * MPP_PINS_PER_REG))
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ctrl_offset = 0x50;
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else
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#endif
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ctrl_offset += 4;
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}
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return (0);
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}
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vm_offset_t
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initarm_lastaddr(void)
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{
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if (fdt_immr_addr(MV_BASE) != 0)
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while (1);
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/* Platform-specific initialisation */
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return (fdt_immr_va - ARM_NOCACHE_KVA_SIZE);
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}
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void
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initarm_gpio_init(void)
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{
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/*
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* Re-initialise MPP. It is important to call this prior to using
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* console as the physical connection can be routed via MPP.
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*/
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if (platform_mpp_init() != 0)
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while (1);
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}
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void
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initarm_late_init(void)
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{
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/*
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* Re-initialise decode windows
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*/
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#if !defined(SOC_MV_FREY)
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if (soc_decode_win() != 0)
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printf("WARNING: could not re-initialise decode windows! "
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"Running with existing settings...\n");
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#else
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/* Disable watchdog and timers */
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write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0);
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#endif
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}
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#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2)
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static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = {
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{ 0, 0, 0, 0, 0, }
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};
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static int
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platform_sram_devmap(struct pmap_devmap *map)
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{
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#if !defined(SOC_MV_ARMADAXP)
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phandle_t child, root;
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u_long base, size;
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/*
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* SRAM range.
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*/
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if ((child = OF_finddevice("/sram")) != 0)
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if (fdt_is_compatible(child, "mrvl,cesa-sram") ||
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fdt_is_compatible(child, "mrvl,scratchpad"))
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goto moveon;
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if ((root = OF_finddevice("/")) == 0)
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return (ENXIO);
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if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 &&
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(child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0)
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goto out;
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moveon:
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if (fdt_regsize(child, &base, &size) != 0)
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return (EINVAL);
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map->pd_va = MV_CESA_SRAM_BASE; /* XXX */
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map->pd_pa = base;
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map->pd_size = size;
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map->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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map->pd_cache = PTE_NOCACHE;
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return (0);
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out:
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#endif
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return (ENOENT);
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}
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/*
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* XXX: When device entry in devmap has pd_size smaller than section size,
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* system will freeze during initialization
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*/
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/*
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* Construct pmap_devmap[] with DT-derived config data.
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*/
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int
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platform_devmap_init(void)
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{
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phandle_t root, child;
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pcell_t bank_count;
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u_long base, size;
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int i, num_mapped;
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i = 0;
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pmap_devmap_bootstrap_table = &fdt_devmap[0];
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/*
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* IMMR range.
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*/
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fdt_devmap[i].pd_va = fdt_immr_va;
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fdt_devmap[i].pd_pa = fdt_immr_pa;
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fdt_devmap[i].pd_size = fdt_immr_size;
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fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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fdt_devmap[i].pd_cache = PTE_NOCACHE;
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i++;
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/*
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* SRAM range.
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*/
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if (i < FDT_DEVMAP_MAX)
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if (platform_sram_devmap(&fdt_devmap[i]) == 0)
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i++;
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/*
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* PCI range(s).
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* PCI range(s) and localbus.
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*/
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if ((root = OF_finddevice("/")) == -1)
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return (ENXIO);
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for (child = OF_child(root); child != 0; child = OF_peer(child)) {
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if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
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/*
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* Check space: each PCI node will consume 2 devmap
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* entries.
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*/
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if (i + 1 >= FDT_DEVMAP_MAX)
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return (ENOMEM);
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/*
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* XXX this should account for PCI and multiple ranges
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* of a given kind.
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*/
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if (fdt_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
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MV_PCI_VA_MEM_BASE) != 0)
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return (ENXIO);
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i += 2;
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}
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if (fdt_is_compatible(child, "mrvl,lbc")) {
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/* Check available space */
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if (OF_getprop(child, "bank-count", (void *)&bank_count,
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sizeof(bank_count)) <= 0)
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/* If no property, use default value */
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bank_count = 1;
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else
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bank_count = fdt32_to_cpu(bank_count);
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if ((i + bank_count) >= FDT_DEVMAP_MAX)
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return (ENOMEM);
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/* Add all localbus ranges to device map */
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num_mapped = 0;
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if (fdt_localbus_devmap(child, &fdt_devmap[i],
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(int)bank_count, &num_mapped) != 0)
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return (ENXIO);
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i += num_mapped;
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}
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}
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/*
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* CESA SRAM range.
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*/
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if ((child = OF_finddevice("sram")) != -1)
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if (fdt_is_compatible(child, "mrvl,cesa-sram"))
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goto moveon;
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if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0)
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/* No CESA SRAM node. */
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return (0);
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moveon:
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if (i >= FDT_DEVMAP_MAX)
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return (ENOMEM);
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if (fdt_regsize(child, &base, &size) != 0)
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return (EINVAL);
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fdt_devmap[i].pd_va = MV_CESA_SRAM_BASE; /* XXX */
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fdt_devmap[i].pd_pa = base;
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fdt_devmap[i].pd_size = size;
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fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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fdt_devmap[i].pd_cache = PTE_NOCACHE;
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return (0);
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}
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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return (NULL);
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}
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int
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bus_dma_get_range_nb(void)
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{
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return (0);
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}
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#if defined(CPU_MV_PJ4B)
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#ifdef DDB
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#include <ddb/ddb.h>
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DB_SHOW_COMMAND(cp15, db_show_cp15)
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{
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u_int reg;
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__asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg));
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db_printf("Cpu ID: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg));
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db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
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__asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg));
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db_printf("Ctrl: 0x%08x\n",reg);
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__asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg));
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db_printf("Aux Ctrl: 0x%08x\n",reg);
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__asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));
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db_printf("Processor Feat 0: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg));
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db_printf("Processor Feat 1: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg));
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db_printf("Debug Feat 0: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg));
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db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg));
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db_printf("Memory Model Feat 0: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg));
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db_printf("Memory Model Feat 1: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg));
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db_printf("Memory Model Feat 2: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg));
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db_printf("Memory Model Feat 3: 0x%08x\n", reg);
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__asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg));
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db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg);
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__asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg));
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db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg);
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__asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg));
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db_printf("CPU ID code extension: 0x%08x\n",reg);
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}
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DB_SHOW_COMMAND(vtop, db_show_vtop)
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{
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u_int reg;
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if (have_addr) {
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__asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr));
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__asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg));
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db_printf("Physical address reg: 0x%08x\n",reg);
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} else
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db_printf("show vtop <virt_addr>\n");
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}
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#endif /* DDB */
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#endif /* CPU_MV_PJ4B */
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