dim 17d956b962 Pull in r230348 from upstream llvm trunk (by Tim Northover): ...

ARM: treat [N x i32] and [N x i64] as AAPCS composite types

  The logic is almost there already, with our special homogeneous
  aggregate handling. Tweaking it like this allows front-ends to emit
  AAPCS compliant code without ever having to count registers or add
  discarded padding arguments.

  Only arrays of i32 and i64 are needed to model AAPCS rules, but I
  decided to apply the logic to all integer arrays for more consistency.

This fixes a possible "Unexpected member type for HA" error when
compiling lib/msun/bsdsrc/b_tgamma.c for armv6.

Reported by:	Jakub Palider <jpa@semihalf.com>

2015-03-23 21:13:29 +00:00

..

AsmPrinter

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SelectionDAG

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AggressiveAntiDepBreaker.cpp

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AggressiveAntiDepBreaker.h

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AllocationOrder.cpp

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AllocationOrder.h

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Analysis.cpp

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AntiDepBreaker.h

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AtomicExpandPass.cpp

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BasicTargetTransformInfo.cpp

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BranchFolding.cpp

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BranchFolding.h

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CalcSpillWeights.cpp

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CallingConvLower.cpp

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CodeGenPrepare.cpp

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CriticalAntiDepBreaker.cpp

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CriticalAntiDepBreaker.h

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DeadMachineInstructionElim.cpp

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DFAPacketizer.cpp

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DwarfEHPrepare.cpp

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EarlyIfConversion.cpp

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EdgeBundles.cpp

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LocalStackSlotAllocation.cpp

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…

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