196 lines
6.9 KiB
C
196 lines
6.9 KiB
C
/*-
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/pmc_mdep.h>
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#include <contrib/octeon-sdk/cvmx.h>
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#include <contrib/octeon-sdk/cvmx-core.h>
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#define OCTEON_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
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PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
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PMC_CAP_THRESHOLD | PMC_CAP_READ | \
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PMC_CAP_WRITE | PMC_CAP_INVERT | \
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PMC_CAP_QUALIFIER)
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const struct mips_event_code_map mips_event_codes[] =
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{
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{ PMC_EV_OCTEON_CLK, MIPS_CTR_ALL, CVMX_CORE_PERF_CLK },
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{ PMC_EV_OCTEON_ISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_ISSUE },
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{ PMC_EV_OCTEON_RET, MIPS_CTR_ALL, CVMX_CORE_PERF_RET },
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{ PMC_EV_OCTEON_NISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_NISSUE },
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{ PMC_EV_OCTEON_SISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_SISSUE },
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{ PMC_EV_OCTEON_DISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_DISSUE },
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{ PMC_EV_OCTEON_IFI, MIPS_CTR_ALL, CVMX_CORE_PERF_IFI },
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{ PMC_EV_OCTEON_BR, MIPS_CTR_ALL, CVMX_CORE_PERF_BR },
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{ PMC_EV_OCTEON_BRMIS, MIPS_CTR_ALL, CVMX_CORE_PERF_BRMIS },
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{ PMC_EV_OCTEON_J, MIPS_CTR_ALL, CVMX_CORE_PERF_J },
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{ PMC_EV_OCTEON_JMIS, MIPS_CTR_ALL, CVMX_CORE_PERF_JMIS },
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{ PMC_EV_OCTEON_REPLAY, MIPS_CTR_ALL, CVMX_CORE_PERF_REPLAY },
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{ PMC_EV_OCTEON_IUNA, MIPS_CTR_ALL, CVMX_CORE_PERF_IUNA },
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{ PMC_EV_OCTEON_TRAP, MIPS_CTR_ALL, CVMX_CORE_PERF_TRAP },
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{ PMC_EV_OCTEON_UULOAD, MIPS_CTR_ALL, CVMX_CORE_PERF_UULOAD },
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{ PMC_EV_OCTEON_UUSTORE, MIPS_CTR_ALL, CVMX_CORE_PERF_UUSTORE },
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{ PMC_EV_OCTEON_ULOAD, MIPS_CTR_ALL, CVMX_CORE_PERF_ULOAD },
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{ PMC_EV_OCTEON_USTORE, MIPS_CTR_ALL, CVMX_CORE_PERF_USTORE },
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{ PMC_EV_OCTEON_EC, MIPS_CTR_ALL, CVMX_CORE_PERF_EC },
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{ PMC_EV_OCTEON_MC, MIPS_CTR_ALL, CVMX_CORE_PERF_MC },
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{ PMC_EV_OCTEON_CC, MIPS_CTR_ALL, CVMX_CORE_PERF_CC },
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{ PMC_EV_OCTEON_CSRC, MIPS_CTR_ALL, CVMX_CORE_PERF_CSRC },
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{ PMC_EV_OCTEON_CFETCH, MIPS_CTR_ALL, CVMX_CORE_PERF_CFETCH },
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{ PMC_EV_OCTEON_CPREF, MIPS_CTR_ALL, CVMX_CORE_PERF_CPREF },
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{ PMC_EV_OCTEON_ICA, MIPS_CTR_ALL, CVMX_CORE_PERF_ICA },
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{ PMC_EV_OCTEON_II, MIPS_CTR_ALL, CVMX_CORE_PERF_II },
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{ PMC_EV_OCTEON_IP, MIPS_CTR_ALL, CVMX_CORE_PERF_IP },
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{ PMC_EV_OCTEON_CIMISS, MIPS_CTR_ALL, CVMX_CORE_PERF_CIMISS },
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{ PMC_EV_OCTEON_WBUF, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUF },
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{ PMC_EV_OCTEON_WDAT, MIPS_CTR_ALL, CVMX_CORE_PERF_WDAT },
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{ PMC_EV_OCTEON_WBUFLD, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFLD },
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{ PMC_EV_OCTEON_WBUFFL, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFFL },
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{ PMC_EV_OCTEON_WBUFTR, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFTR },
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{ PMC_EV_OCTEON_BADD, MIPS_CTR_ALL, CVMX_CORE_PERF_BADD },
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{ PMC_EV_OCTEON_BADDL2, MIPS_CTR_ALL, CVMX_CORE_PERF_BADDL2 },
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{ PMC_EV_OCTEON_BFILL, MIPS_CTR_ALL, CVMX_CORE_PERF_BFILL },
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{ PMC_EV_OCTEON_DDIDS, MIPS_CTR_ALL, CVMX_CORE_PERF_DDIDS },
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{ PMC_EV_OCTEON_IDIDS, MIPS_CTR_ALL, CVMX_CORE_PERF_IDIDS },
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{ PMC_EV_OCTEON_DIDNA, MIPS_CTR_ALL, CVMX_CORE_PERF_DIDNA },
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{ PMC_EV_OCTEON_LDS, MIPS_CTR_ALL, CVMX_CORE_PERF_LDS },
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{ PMC_EV_OCTEON_LMLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_LMLDS },
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{ PMC_EV_OCTEON_IOLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_IOLDS },
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{ PMC_EV_OCTEON_DMLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_DMLDS },
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{ PMC_EV_OCTEON_STS, MIPS_CTR_ALL, CVMX_CORE_PERF_STS },
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{ PMC_EV_OCTEON_LMSTS, MIPS_CTR_ALL, CVMX_CORE_PERF_LMSTS },
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{ PMC_EV_OCTEON_IOSTS, MIPS_CTR_ALL, CVMX_CORE_PERF_IOSTS },
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{ PMC_EV_OCTEON_IOBDMA, MIPS_CTR_ALL, CVMX_CORE_PERF_IOBDMA },
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{ PMC_EV_OCTEON_DTLB, MIPS_CTR_ALL, CVMX_CORE_PERF_DTLB },
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{ PMC_EV_OCTEON_DTLBAD, MIPS_CTR_ALL, CVMX_CORE_PERF_DTLBAD },
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{ PMC_EV_OCTEON_ITLB, MIPS_CTR_ALL, CVMX_CORE_PERF_ITLB },
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{ PMC_EV_OCTEON_SYNC, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNC },
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{ PMC_EV_OCTEON_SYNCIOB, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNCIOB },
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{ PMC_EV_OCTEON_SYNCW, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNCW },
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};
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const int mips_event_codes_size = nitems(mips_event_codes);
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struct mips_pmc_spec mips_pmc_spec = {
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.ps_cpuclass = PMC_CLASS_OCTEON,
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.ps_cputype = PMC_CPU_MIPS_OCTEON,
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.ps_capabilities = OCTEON_PMC_CAPS,
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.ps_counter_width = 64
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};
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/*
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* Performance Count Register N
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*/
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uint64_t
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mips_pmcn_read(unsigned int pmc)
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{
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uint64_t reg = 0;
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KASSERT(pmc < mips_npmcs, ("[mips,%d] illegal PMC number %d",
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__LINE__, pmc));
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/* The counter value is the next value after the control register. */
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switch (pmc) {
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case 0:
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CVMX_MF_COP0(reg, COP0_PERFVALUE0);
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break;
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case 1:
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CVMX_MF_COP0(reg, COP0_PERFVALUE1);
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break;
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default:
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return 0;
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}
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return (reg);
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}
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uint64_t
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mips_pmcn_write(unsigned int pmc, uint64_t reg)
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{
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KASSERT(pmc < mips_npmcs, ("[mips,%d] illegal PMC number %d",
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__LINE__, pmc));
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switch (pmc) {
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case 0:
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CVMX_MT_COP0(reg, COP0_PERFVALUE0);
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break;
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case 1:
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CVMX_MT_COP0(reg, COP0_PERFVALUE1);
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break;
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default:
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return 0;
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}
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return (reg);
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}
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uint32_t
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mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps)
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{
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cvmx_core_perf_control_t control;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[mips,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < mips_npmcs,
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("[mips,%d] illegal row index %d", __LINE__, ri));
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control.s.event = event;
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if (caps & PMC_CAP_SYSTEM) {
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control.s.k = 1;
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control.s.s = 1;
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control.s.ex = 1;
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}
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if (caps & PMC_CAP_USER)
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control.s.u = 1;
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if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) {
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control.s.k = 1;
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control.s.s = 1;
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control.s.u = 1;
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control.s.ex = 1;
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}
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if (caps & PMC_CAP_INTERRUPT)
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control.s.ie = 1;
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PMCDBG2(MDP,ALL,2,"mips-allocate ri=%d -> config=0x%x", ri,
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control.u32);
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return (control.u32);
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}
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