0757a4afb5
The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
20 lines
300 B
Plaintext
20 lines
300 B
Plaintext
# $FreeBSD$
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# Options specific to the powerpc platform kernels
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AIM opt_global.h
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E500 opt_global.h
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FPU_EMU
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GFB_DEBUG opt_gfb.h
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GFB_NO_FONT_LOADING opt_gfb.h
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GFB_NO_MODE_CHANGE opt_gfb.h
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POWERMAC opt_platform.h
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MPC85XX opt_platform.h
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PSIM
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SC_OFWFB opt_ofwfb.h
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OFWCONS_POLL_HZ opt_ofw.h
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