817 lines
20 KiB
C
817 lines
20 KiB
C
/*
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* Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
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* Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/pcm/ac97.h>
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#include <dev/sound/pci/ich.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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SND_DECLARE_FILE("$FreeBSD$");
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/* -------------------------------------------------------------------- */
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#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
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#define ICH_DTBL_LENGTH 32
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#define ICH_DEFAULT_BUFSZ 16384
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#define ICH_MAX_BUFSZ 65536
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#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */
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/* buffer descriptor */
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struct ich_desc {
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volatile u_int32_t buffer;
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volatile u_int32_t length;
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};
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struct sc_info;
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/* channel registers */
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struct sc_chinfo {
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u_int32_t num:8, run:1, run_save:1;
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u_int32_t blksz, blkcnt, spd;
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u_int32_t regbase, spdreg;
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u_int32_t imask;
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u_int32_t civ;
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct sc_info *parent;
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struct ich_desc *dtbl;
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};
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/* device private data */
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struct sc_info {
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device_t dev;
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int hasvra, hasvrm, hasmic;
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unsigned int chnum, bufsz;
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int sample_size, swap_reg;
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struct resource *nambar, *nabmbar, *irq;
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int nambarid, nabmbarid, irqid;
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bus_space_tag_t nambart, nabmbart;
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bus_space_handle_t nambarh, nabmbarh;
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bus_dma_tag_t dmat;
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bus_dmamap_t dtmap;
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void *ih;
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struct ac97_info *codec;
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struct sc_chinfo ch[3];
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int ac97rate;
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struct ich_desc *dtbl;
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};
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/* -------------------------------------------------------------------- */
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static u_int32_t ich_fmt[] = {
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AFMT_STEREO | AFMT_S16_LE,
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0
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};
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static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
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static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
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/* -------------------------------------------------------------------- */
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/* Hardware */
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static u_int32_t
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ich_rd(struct sc_info *sc, int regno, int size)
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{
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switch (size) {
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case 1:
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return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno);
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case 2:
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return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno);
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case 4:
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return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno);
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default:
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return 0xffffffff;
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}
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}
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static void
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ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
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{
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switch (size) {
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case 1:
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bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
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break;
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case 2:
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bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
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break;
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case 4:
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bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
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break;
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}
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}
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/* ac97 codec */
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static int
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ich_waitcd(void *devinfo)
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{
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int i;
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u_int32_t data;
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struct sc_info *sc = (struct sc_info *)devinfo;
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for (i = 0; i < ICH_TIMEOUT; i++) {
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data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
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if ((data & 0x01) == 0)
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return 0;
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}
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device_printf(sc->dev, "CODEC semaphore timeout\n");
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return ETIMEDOUT;
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}
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static int
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ich_rdcd(kobj_t obj, void *devinfo, int regno)
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{
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struct sc_info *sc = (struct sc_info *)devinfo;
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regno &= 0xff;
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ich_waitcd(sc);
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return bus_space_read_2(sc->nambart, sc->nambarh, regno);
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}
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static int
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ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data)
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{
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struct sc_info *sc = (struct sc_info *)devinfo;
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regno &= 0xff;
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ich_waitcd(sc);
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bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
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return 0;
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}
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static kobj_method_t ich_ac97_methods[] = {
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KOBJMETHOD(ac97_read, ich_rdcd),
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KOBJMETHOD(ac97_write, ich_wrcd),
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{ 0, 0 }
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};
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AC97_DECLARE(ich_ac97);
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/* -------------------------------------------------------------------- */
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/* common routines */
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static void
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ich_filldtbl(struct sc_chinfo *ch)
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{
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u_int32_t base;
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int i;
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base = vtophys(sndbuf_getbuf(ch->buffer));
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ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz;
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if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) {
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ch->blkcnt = 2;
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ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt;
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}
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for (i = 0; i < ICH_DTBL_LENGTH; i++) {
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ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
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ch->dtbl[i].length = ICH_BDC_IOC
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| (ch->blksz / ch->parent->sample_size);
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}
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}
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static int
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ich_resetchan(struct sc_info *sc, int num)
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{
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int i, cr, regbase;
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if (num == 0)
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regbase = ICH_REG_PO_BASE;
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else if (num == 1)
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regbase = ICH_REG_PI_BASE;
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else if (num == 2)
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regbase = ICH_REG_MC_BASE;
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else
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return ENXIO;
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ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
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DELAY(100);
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ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
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for (i = 0; i < ICH_TIMEOUT; i++) {
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cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
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if (cr == 0)
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return 0;
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}
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device_printf(sc->dev, "cannot reset channel %d\n", num);
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return ENXIO;
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}
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/* -------------------------------------------------------------------- */
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/* channel interface */
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static void *
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ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
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{
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struct sc_info *sc = devinfo;
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struct sc_chinfo *ch;
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unsigned int num;
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num = sc->chnum++;
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ch = &sc->ch[num];
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ch->num = num;
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ch->buffer = b;
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ch->channel = c;
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ch->parent = sc;
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ch->run = 0;
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ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
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ch->blkcnt = 2;
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ch->blksz = sc->bufsz / ch->blkcnt;
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switch(ch->num) {
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case 0: /* play */
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KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
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ch->regbase = ICH_REG_PO_BASE;
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ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0;
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ch->imask = ICH_GLOB_STA_POINT;
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break;
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case 1: /* record */
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KASSERT(dir == PCMDIR_REC, ("wrong direction"));
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ch->regbase = ICH_REG_PI_BASE;
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ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0;
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ch->imask = ICH_GLOB_STA_PIINT;
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break;
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case 2: /* mic */
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KASSERT(dir == PCMDIR_REC, ("wrong direction"));
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ch->regbase = ICH_REG_MC_BASE;
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ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0;
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ch->imask = ICH_GLOB_STA_MINT;
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break;
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default:
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return NULL;
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}
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if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz))
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return NULL;
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ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
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return ch;
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}
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static int
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ichchan_setformat(kobj_t obj, void *data, u_int32_t format)
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{
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return 0;
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}
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static int
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ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
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{
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struct sc_chinfo *ch = data;
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struct sc_info *sc = ch->parent;
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if (ch->spdreg) {
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int r;
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if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
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sc->ac97rate = 48000;
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r = (speed * 48000) / sc->ac97rate;
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/*
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* Cast the return value of ac97_setrate() to u_int so that
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* the math don't overflow into the negative range.
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*/
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ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) *
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sc->ac97rate) / 48000;
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} else {
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ch->spd = 48000;
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}
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return ch->spd;
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}
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static int
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ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
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{
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struct sc_chinfo *ch = data;
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struct sc_info *sc = ch->parent;
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ch->blksz = blocksize;
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ich_filldtbl(ch);
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ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
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return ch->blksz;
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}
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static int
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ichchan_trigger(kobj_t obj, void *data, int go)
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{
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struct sc_chinfo *ch = data;
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struct sc_info *sc = ch->parent;
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switch (go) {
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case PCMTRIG_START:
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ch->run = 1;
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ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
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ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
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break;
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case PCMTRIG_ABORT:
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ich_resetchan(sc, ch->num);
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ch->run = 0;
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break;
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}
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return 0;
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}
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static int
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ichchan_getptr(kobj_t obj, void *data)
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{
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struct sc_chinfo *ch = data;
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struct sc_info *sc = ch->parent;
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u_int32_t pos;
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ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
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pos = ch->civ * ch->blksz;
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return pos;
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}
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static struct pcmchan_caps *
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ichchan_getcaps(kobj_t obj, void *data)
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{
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struct sc_chinfo *ch = data;
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return ch->spdreg? &ich_vrcaps : &ich_caps;
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}
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static kobj_method_t ichchan_methods[] = {
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KOBJMETHOD(channel_init, ichchan_init),
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KOBJMETHOD(channel_setformat, ichchan_setformat),
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KOBJMETHOD(channel_setspeed, ichchan_setspeed),
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KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
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KOBJMETHOD(channel_trigger, ichchan_trigger),
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KOBJMETHOD(channel_getptr, ichchan_getptr),
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KOBJMETHOD(channel_getcaps, ichchan_getcaps),
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{ 0, 0 }
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};
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CHANNEL_DECLARE(ichchan);
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/* -------------------------------------------------------------------- */
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/* The interrupt handler */
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static void
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ich_intr(void *p)
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{
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struct sc_info *sc = (struct sc_info *)p;
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struct sc_chinfo *ch;
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u_int32_t cbi, lbi, lvi, st, gs;
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int i;
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gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
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if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
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/* Clear resume interrupt(s) - nothing doing with them */
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ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
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}
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gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
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for (i = 0; i < 3; i++) {
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ch = &sc->ch[i];
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if ((ch->imask & gs) == 0)
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continue;
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gs &= ~ch->imask;
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st = ich_rd(sc, ch->regbase +
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(sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
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2);
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st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
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if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
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/* block complete - update buffer */
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if (ch->run)
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chn_intr(ch->channel);
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lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
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cbi = ch->civ % ch->blkcnt;
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if (cbi == 0)
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cbi = ch->blkcnt - 1;
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else
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cbi--;
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lbi = lvi % ch->blkcnt;
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if (cbi >= lbi)
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lvi += cbi - lbi;
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else
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lvi += cbi + ch->blkcnt - lbi;
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lvi %= ICH_DTBL_LENGTH;
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ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
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}
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/* clear status bit */
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ich_wr(sc, ch->regbase +
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(sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
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st, 2);
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}
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if (gs != 0) {
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device_printf(sc->dev,
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"Unhandled interrupt, gs_intr = %x\n", gs);
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}
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}
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/* ------------------------------------------------------------------------- */
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/* Sysctl to control ac97 speed (some boards overclocked ac97). */
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static int
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ich_initsys(struct sc_info* sc)
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{
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#ifdef SND_DYNSYSCTL
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SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
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SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
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OID_AUTO, "ac97rate", CTLFLAG_RW,
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&sc->ac97rate, 48000,
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"AC97 link rate (default = 48000)");
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#endif /* SND_DYNSYSCTL */
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return 0;
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}
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/* -------------------------------------------------------------------- */
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/* Calibrate card (some boards are overclocked and need scaling) */
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static
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unsigned int ich_calibrate(struct sc_info *sc)
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{
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struct sc_chinfo *ch = &sc->ch[1];
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struct timeval t1, t2;
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u_int8_t ociv, nciv;
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u_int32_t wait_us, actual_48k_rate, bytes;
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/*
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* Grab audio from input for fixed interval and compare how
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* much we actually get with what we expect. Interval needs
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* to be sufficiently short that no interrupts are
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* generated.
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*/
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KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
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bytes = sndbuf_getsize(ch->buffer) / 2;
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ichchan_setblocksize(0, ch, bytes);
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/*
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* our data format is stereo, 16 bit so each sample is 4 bytes.
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* assuming we get 48000 samples per second, we get 192000 bytes/sec.
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* we're going to start recording with interrupts disabled and measure
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* the time taken for one block to complete. we know the block size,
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* we know the time in microseconds, we calculate the sample rate:
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*
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* actual_rate [bps] = bytes / (time [s] * 4)
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* actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
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* actual_rate [Hz] = (bytes * 250000) / time [us]
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*/
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/* prepare */
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ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
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nciv = ociv;
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ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
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/* start */
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microtime(&t1);
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ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
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/* wait */
|
|
while (nciv == ociv) {
|
|
microtime(&t2);
|
|
if (t2.tv_sec - t1.tv_sec > 1)
|
|
break;
|
|
nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
|
|
}
|
|
microtime(&t2);
|
|
|
|
/* stop */
|
|
ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
|
|
|
|
/* reset */
|
|
DELAY(100);
|
|
ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
|
|
|
|
/* turn time delta into us */
|
|
wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
|
|
|
|
if (nciv == ociv) {
|
|
device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
|
|
return 0;
|
|
}
|
|
|
|
actual_48k_rate = (bytes * 250000) / wait_us;
|
|
|
|
if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
|
|
sc->ac97rate = actual_48k_rate;
|
|
} else {
|
|
sc->ac97rate = 48000;
|
|
}
|
|
|
|
if (bootverbose || sc->ac97rate != 48000) {
|
|
device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
|
|
if (sc->ac97rate != actual_48k_rate)
|
|
printf(", will use %d Hz", sc->ac97rate);
|
|
printf("\n");
|
|
}
|
|
|
|
return sc->ac97rate;
|
|
}
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/* Probe and attach the card */
|
|
|
|
static void
|
|
ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
|
|
{
|
|
return;
|
|
}
|
|
|
|
static int
|
|
ich_init(struct sc_info *sc)
|
|
{
|
|
u_int32_t stat;
|
|
int sz;
|
|
|
|
ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
|
|
DELAY(600000);
|
|
stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
|
|
|
|
if ((stat & ICH_GLOB_STA_PCR) == 0)
|
|
return ENXIO;
|
|
|
|
ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
|
|
|
|
if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
|
|
return ENXIO;
|
|
if (sc->hasmic && ich_resetchan(sc, 2))
|
|
return ENXIO;
|
|
|
|
if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap))
|
|
return ENOSPC;
|
|
|
|
sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3;
|
|
if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) {
|
|
bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap);
|
|
return ENOSPC;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ich_pci_probe(device_t dev)
|
|
{
|
|
switch(pci_get_devid(dev)) {
|
|
case 0x71958086:
|
|
device_set_desc(dev, "Intel 443MX");
|
|
return 0;
|
|
|
|
case 0x24158086:
|
|
device_set_desc(dev, "Intel 82801AA (ICH)");
|
|
return 0;
|
|
|
|
case 0x24258086:
|
|
device_set_desc(dev, "Intel 82801AB (ICH)");
|
|
return 0;
|
|
|
|
case 0x24458086:
|
|
device_set_desc(dev, "Intel 82801BA (ICH2)");
|
|
return 0;
|
|
|
|
case 0x24858086:
|
|
device_set_desc(dev, "Intel 82801CA (ICH3)");
|
|
return 0;
|
|
|
|
case SIS7012ID:
|
|
device_set_desc(dev, "SiS 7012");
|
|
return 0;
|
|
|
|
case 0x01b110de:
|
|
device_set_desc(dev, "Nvidia nForce AC97 controller");
|
|
return 0;
|
|
|
|
default:
|
|
return ENXIO;
|
|
}
|
|
}
|
|
|
|
static int
|
|
ich_pci_attach(device_t dev)
|
|
{
|
|
u_int32_t data;
|
|
u_int16_t extcaps;
|
|
struct sc_info *sc;
|
|
char status[SND_STATUSLEN];
|
|
|
|
if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
|
|
device_printf(dev, "cannot allocate softc\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
bzero(sc, sizeof(*sc));
|
|
sc->dev = dev;
|
|
|
|
/*
|
|
* The SiS 7012 register set isn't quite like the standard ich.
|
|
* There really should be a general "quirks" mechanism.
|
|
*/
|
|
if (pci_get_devid(dev) == SIS7012ID) {
|
|
sc->swap_reg = 1;
|
|
sc->sample_size = 1;
|
|
} else {
|
|
sc->swap_reg = 0;
|
|
sc->sample_size = 2;
|
|
}
|
|
|
|
data = pci_read_config(dev, PCIR_COMMAND, 2);
|
|
data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
|
|
pci_write_config(dev, PCIR_COMMAND, data, 2);
|
|
data = pci_read_config(dev, PCIR_COMMAND, 2);
|
|
|
|
sc->nambarid = PCIR_NAMBAR;
|
|
sc->nabmbarid = PCIR_NABMBAR;
|
|
sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE);
|
|
sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE);
|
|
|
|
if (!sc->nambar || !sc->nabmbar) {
|
|
device_printf(dev, "unable to map IO port space\n");
|
|
goto bad;
|
|
}
|
|
|
|
sc->nambart = rman_get_bustag(sc->nambar);
|
|
sc->nambarh = rman_get_bushandle(sc->nambar);
|
|
sc->nabmbart = rman_get_bustag(sc->nabmbar);
|
|
sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
|
|
|
|
sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
|
|
if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
|
|
NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) {
|
|
device_printf(dev, "unable to create dma tag\n");
|
|
goto bad;
|
|
}
|
|
|
|
sc->irqid = 0;
|
|
sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
|
|
if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) {
|
|
device_printf(dev, "unable to map interrupt\n");
|
|
goto bad;
|
|
}
|
|
|
|
if (ich_init(sc)) {
|
|
device_printf(dev, "unable to initialize the card\n");
|
|
goto bad;
|
|
}
|
|
|
|
sc->codec = AC97_CREATE(dev, sc, ich_ac97);
|
|
if (sc->codec == NULL)
|
|
goto bad;
|
|
mixer_init(dev, ac97_getmixerclass(), sc->codec);
|
|
|
|
/* check and set VRA function */
|
|
extcaps = ac97_getextcaps(sc->codec);
|
|
sc->hasvra = extcaps & AC97_EXTCAP_VRA;
|
|
sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
|
|
sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL;
|
|
ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
|
|
|
|
if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1))
|
|
goto bad;
|
|
|
|
pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
|
|
pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
|
|
if (sc->hasmic)
|
|
pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
|
|
|
|
snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u",
|
|
rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz);
|
|
|
|
pcm_setstatus(dev, status);
|
|
|
|
ich_initsys(sc);
|
|
ich_calibrate(sc);
|
|
|
|
return 0;
|
|
|
|
bad:
|
|
if (sc->codec)
|
|
ac97_destroy(sc->codec);
|
|
if (sc->ih)
|
|
bus_teardown_intr(dev, sc->irq, sc->ih);
|
|
if (sc->irq)
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
|
|
if (sc->nambar)
|
|
bus_release_resource(dev, SYS_RES_IOPORT,
|
|
sc->nambarid, sc->nambar);
|
|
if (sc->nabmbar)
|
|
bus_release_resource(dev, SYS_RES_IOPORT,
|
|
sc->nabmbarid, sc->nabmbar);
|
|
free(sc, M_DEVBUF);
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
ich_pci_detach(device_t dev)
|
|
{
|
|
struct sc_info *sc;
|
|
int r;
|
|
|
|
r = pcm_unregister(dev);
|
|
if (r)
|
|
return r;
|
|
sc = pcm_getdevinfo(dev);
|
|
|
|
bus_teardown_intr(dev, sc->irq, sc->ih);
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
|
|
bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar);
|
|
bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar);
|
|
bus_dma_tag_destroy(sc->dmat);
|
|
free(sc, M_DEVBUF);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ich_pci_suspend(device_t dev)
|
|
{
|
|
struct sc_info *sc;
|
|
int i;
|
|
|
|
sc = pcm_getdevinfo(dev);
|
|
for (i = 0 ; i < 3; i++) {
|
|
sc->ch[i].run_save = sc->ch[i].run;
|
|
if (sc->ch[i].run) {
|
|
ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ich_pci_resume(device_t dev)
|
|
{
|
|
struct sc_info *sc;
|
|
int i;
|
|
|
|
sc = pcm_getdevinfo(dev);
|
|
|
|
/* Reinit audio device */
|
|
if (ich_init(sc) == -1) {
|
|
device_printf(dev, "unable to reinitialize the card\n");
|
|
return ENXIO;
|
|
}
|
|
/* Reinit mixer */
|
|
if (mixer_reinit(dev) == -1) {
|
|
device_printf(dev, "unable to reinitialize the mixer\n");
|
|
return ENXIO;
|
|
}
|
|
/* Re-start DMA engines */
|
|
for (i = 0 ; i < 3; i++) {
|
|
struct sc_chinfo *ch = &sc->ch[i];
|
|
if (sc->ch[i].run_save) {
|
|
ichchan_setblocksize(0, ch, ch->blksz);
|
|
ichchan_setspeed(0, ch, ch->spd);
|
|
ichchan_trigger(0, ch, PCMTRIG_START);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static device_method_t ich_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, ich_pci_probe),
|
|
DEVMETHOD(device_attach, ich_pci_attach),
|
|
DEVMETHOD(device_detach, ich_pci_detach),
|
|
DEVMETHOD(device_suspend, ich_pci_suspend),
|
|
DEVMETHOD(device_resume, ich_pci_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t ich_driver = {
|
|
"pcm",
|
|
ich_methods,
|
|
PCM_SOFTC_SIZE,
|
|
};
|
|
|
|
DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
|
|
MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
|
|
MODULE_VERSION(snd_ich, 1);
|