Andrew Turner 062c276886 Add support for multiple GICv3 ITS devices. For this we add sc_irq_base ...

and sc_irq_length to the softc to handle the base number of IRQs available,
make gicv3_get_nirqs return the number of available interrupt IDs, and
limit which CPUs we send interrupts to based on the numa domain.

The last point is only strictly needed on a dual socket ThunderX where we
are unable to send MSI/MSI-X interrupts between sockets.

Sponsored by:	DARPA, AFRL

2017-08-13 18:54:51 +00:00

..

acpica

Add support to find the arm64 serial using the ACPI tables. This uses the

2016-11-21 19:26:58 +00:00

arm64

Add support for multiple GICv3 ITS devices. For this we add sc_irq_base

2017-08-13 18:54:51 +00:00

cavium

If ofw_bus_msimap fails don't try to use the invalid MSI/MSI-X parent node.

2017-03-16 17:49:37 +00:00

cloudabi64

Move struct syscall_args syscall arguments parameters container into

2017-06-12 21:03:23 +00:00

conf

arm64: Add Allwinner H5 SoC

2017-08-02 20:19:19 +00:00

include

Reliably enable debug exceptions on all CPUs.

2017-08-12 18:42:54 +00:00