John Baldwin 7e4af296b3 - Add a member to the atpic interrupt source structures to indicate if the
IRQ is edge triggered or level triggered.  For ISA interrupts, we assume
  that edge triggered interrupts are always active high and that level
  triggered interrupts are always active low.
- Don't disable an edge triggered interrupt in the PIC.  This avoids
  outb instructions to the actual PIC for traditional ISA IRQs such as
  IRQ 1, 6, 14, and 15.  (Fast interrupts such as IRQs 0 and 8 don't mask
  their source, so this doesn't change anything for them.)
- For MCA systems we assume that all interrupts are level triggered and
  thus need masking.  Otherwise, we probe the ELCR.  If it exists we trust
  what it tells us regarding which interrupts are level triggered.  If it
  does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered
  and that all other IRQs are level triggered and need masking.
- Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
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2004-02-21 21:10:55 +00:00
2003-06-02 16:32:55 +00:00
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2003-06-02 16:32:55 +00:00
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2004-02-21 21:10:55 +00:00