adrian 7f1fba1154 Add missing \n. ...

Otherwise you end up with:

Cache info:
  picache_stride    = 4096
  picache_loopcount = 16
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: MIPS Technologies processor v80.150
  MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
  L1 i-cache: 4 ways of 512 sets, 32 bytes per line
  L1 d-cache: 4 ways of 256 sets, 32 bytes per line
  L2 cache: disabled  Config1=0xbee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
  Config2=0x80000000
  Config3=0x2420

Tested:

* MT7620 SoC

2015-12-24 04:37:19 +00:00

..

adm5120

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

alchemy

…

atheros

[qca953x] remove unneeded initialisation.

2015-12-15 04:45:00 +00:00

beri

preload_search_info: make sure mod is set

2015-08-21 15:57:57 +00:00

cavium

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

conf

Add support for the integrated wifi for the QCA953x base config and

2015-11-29 05:49:49 +00:00

gxemul

…

idt

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

include

[mips] Add TLB pagemask probing code, and print out the allowable page sizes.

2015-12-22 15:59:41 +00:00

malta

[mips]: Don't hard-code PHYS_AVAIL_ENTRIES.

2015-11-22 02:40:19 +00:00

mips

Add missing \n.

2015-12-24 04:37:19 +00:00

nlm

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

rmi

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

rt305x

Add support for the uart classes to set their default register shift value.

2015-04-11 17:16:23 +00:00

sentry5

…

sibyte

…