635 lines
18 KiB
C
635 lines
18 KiB
C
/******************************************************************************
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Copyright (c) 2001-2015, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _IF_IGB_H_
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#define _IF_IGB_H_
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#ifdef ALTQ
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#define IGB_LEGACY_TX
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#endif
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#include <sys/param.h>
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#include <sys/systm.h>
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#ifndef IGB_LEGACY_TX
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#include <sys/buf_ring.h>
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#endif
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <sys/eventhandler.h>
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#include <sys/pcpu.h>
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#include <sys/smp.h>
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#include <machine/smp.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <net/bpf.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#ifdef RSS
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#include <net/rss_config.h>
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#include <netinet/in_rss.h>
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#endif
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#include <net/if_types.h>
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#include <net/if_vlan_var.h>
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#include <netinet/in_systm.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <netinet/ip.h>
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#include <netinet/ip6.h>
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#include <netinet/tcp.h>
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#include <netinet/tcp_lro.h>
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#include <netinet/udp.h>
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#include <machine/in_cksum.h>
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#include <dev/led/led.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include "e1000_api.h"
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#include "e1000_82575.h"
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/* Tunables */
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/*
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* IGB_TXD: Maximum number of Transmit Descriptors
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*
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* This value is the number of transmit descriptors allocated by the driver.
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* Increasing this value allows the driver to queue more transmits. Each
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* descriptor is 16 bytes.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define IGB_MIN_TXD 256
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#define IGB_DEFAULT_TXD 1024
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#define IGB_MAX_TXD 4096
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/*
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* IGB_RXD: Maximum number of Receive Descriptors
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*
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* This value is the number of receive descriptors allocated by the driver.
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* Increasing this value allows the driver to buffer more incoming packets.
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* Each descriptor is 16 bytes. A receive buffer is also allocated for each
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* descriptor. The maximum MTU size is 16110.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define IGB_MIN_RXD 256
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#define IGB_DEFAULT_RXD 1024
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#define IGB_MAX_RXD 4096
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/*
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* IGB_TIDV - Transmit Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value delays the generation of transmit interrupts in units of
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* 1.024 microseconds. Transmit interrupt reduction can improve CPU
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* efficiency if properly tuned for specific network traffic. If the
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* system is reporting dropped transmits, this value may be set too high
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* causing the driver to run out of available transmit descriptors.
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*/
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#define IGB_TIDV 64
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/*
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* IGB_TADV - Transmit Absolute Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* transmit interrupt is generated. Useful only if IGB_TIDV is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is sent on the wire within the set amount of time. Proper tuning,
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* along with IGB_TIDV, may improve traffic throughput in specific
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* network conditions.
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*/
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#define IGB_TADV 64
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/*
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* IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 0
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* This value delays the generation of receive interrupts in units of 1.024
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* microseconds. Receive interrupt reduction can improve CPU efficiency if
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* properly tuned for specific network traffic. Increasing this value adds
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* extra latency to frame reception and can end up decreasing the throughput
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* of TCP traffic. If the system is reporting dropped receives, this value
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* may be set too high, causing the driver to run out of available receive
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* descriptors.
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*
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* CAUTION: When setting IGB_RDTR to a value other than 0, adapters
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* may hang (stop transmitting) under certain network conditions.
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* If this occurs a WATCHDOG message is logged in the system
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* event log. In addition, the controller is automatically reset,
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* restoring the network connection. To eliminate the potential
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* for the hang ensure that IGB_RDTR is set to 0.
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*/
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#define IGB_RDTR 0
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/*
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* Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* receive interrupt is generated. Useful only if IGB_RDTR is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is received within the set amount of time. Proper tuning,
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* along with IGB_RDTR, may improve traffic throughput in specific network
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* conditions.
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*/
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#define IGB_RADV 64
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/*
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* This parameter controls the duration of transmit watchdog timer.
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*/
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#define IGB_WATCHDOG (10 * hz)
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/*
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* This parameter controls when the driver calls the routine to reclaim
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* transmit descriptors. Cleaning earlier seems a win.
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*/
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#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2)
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/*
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* This parameter controls whether or not autonegotation is enabled.
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* 0 - Disable autonegotiation
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* 1 - Enable autonegotiation
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*/
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#define DO_AUTO_NEG 1
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/*
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* This parameter control whether or not the driver will wait for
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* autonegotiation to complete.
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* 1 - Wait for autonegotiation to complete
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* 0 - Don't wait for autonegotiation to complete
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*/
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#define WAIT_FOR_AUTO_NEG_DEFAULT 0
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/* Tunables -- End */
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#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
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ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
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ADVERTISE_1000_FULL)
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#define AUTO_ALL_MODES 0
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/* PHY master/slave setting */
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#define IGB_MASTER_SLAVE e1000_ms_hw_default
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/* Support AutoMediaDetect for Marvell M88 PHY in i354 */
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#define IGB_MEDIA_RESET (1 << 0)
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/*
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* Micellaneous constants
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*/
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#define IGB_INTEL_VENDOR_ID 0x8086
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#define IGB_JUMBO_PBA 0x00000028
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#define IGB_DEFAULT_PBA 0x00000030
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#define IGB_SMARTSPEED_DOWNSHIFT 3
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#define IGB_SMARTSPEED_MAX 15
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#define IGB_MAX_LOOP 10
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#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \
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((hw->mac.type <= e1000_82576) ? 16 : 8))
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#define IGB_RX_HTHRESH 8
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#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
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adapter->msix_mem) ? 1 : 4)
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#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
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#define IGB_TX_HTHRESH 1
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#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \
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adapter->msix_mem) ? 1 : 16)
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#define MAX_NUM_MULTICAST_ADDRESSES 128
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#define PCI_ANY_ID (~0U)
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#define ETHER_ALIGN 2
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#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514)
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#define IGB_FC_PAUSE_TIME 0x0680
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#define IGB_EEPROM_APME 0x400;
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/* Queue minimum free for use */
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#define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8)
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/*
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* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
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* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
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* also optimize cache line size effect. H/W supports up to cache line size 128.
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*/
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#define IGB_DBA_ALIGN 128
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#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
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/* PCI Config defines */
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#define IGB_MSIX_BAR 3
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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#define DEBUG_IOCTL 0
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#define DEBUG_HW 0
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#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
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#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
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#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
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#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
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#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
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#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
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#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
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#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
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#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
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#define IGB_MAX_SCATTER 40
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#define IGB_VFTA_SIZE 128
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#define IGB_BR_SIZE 4096 /* ring buf size */
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#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
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#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
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#define IGB_TXPBSIZE 20408
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#define IGB_HDR_BUF 128
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#define IGB_PKTTYPE_MASK 0x0000FFF0
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#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */
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#define ETH_ZLEN 60
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#define ETH_ADDR_LEN 6
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/* Offload bits in mbuf flag */
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#if __FreeBSD_version >= 1000000
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#define CSUM_OFFLOAD_IPV4 (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP|CSUM_IP_SCTP)
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#define CSUM_OFFLOAD_IPV6 (CSUM_IP6_TCP|CSUM_IP6_UDP|CSUM_IP6_SCTP)
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#define CSUM_OFFLOAD (CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6)
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#elif __FreeBSD_version >= 800000
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#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
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#else
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#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
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#endif
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/* Define the starting Interrupt rate per Queue */
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#define IGB_INTS_PER_SEC 8000
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#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2)
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#define IGB_LINK_ITR 2000
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#define I210_LINK_DELAY 1000
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/* Precision Time Sync (IEEE 1588) defines */
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#define ETHERTYPE_IEEE1588 0x88F7
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#define PICOSECS_PER_TICK 20833
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#define TSYNC_PORT 319 /* UDP port for the protocol */
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/*
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* Bus dma allocation structure used by
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* e1000_dma_malloc and e1000_dma_free.
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*/
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struct igb_dma_alloc {
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bus_addr_t dma_paddr;
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caddr_t dma_vaddr;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_dma_segment_t dma_seg;
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int dma_nseg;
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};
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/*
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** Driver queue struct: this is the interrupt container
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** for the associated tx and rx ring.
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*/
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struct igb_queue {
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struct adapter *adapter;
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u32 msix; /* This queue's MSIX vector */
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u32 eims; /* This queue's EIMS bit */
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u32 eitr_setting;
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struct resource *res;
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void *tag;
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struct tx_ring *txr;
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struct rx_ring *rxr;
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struct task que_task;
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struct taskqueue *tq;
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u64 irqs;
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};
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/*
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* The transmit ring, one per queue
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*/
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struct tx_ring {
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struct adapter *adapter;
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struct mtx tx_mtx;
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u32 me;
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int watchdog_time;
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union e1000_adv_tx_desc *tx_base;
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struct igb_tx_buf *tx_buffers;
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struct igb_dma_alloc txdma;
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volatile u16 tx_avail;
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u16 next_avail_desc;
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u16 next_to_clean;
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u16 num_desc;
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enum {
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IGB_QUEUE_IDLE = 1,
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IGB_QUEUE_WORKING = 2,
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IGB_QUEUE_HUNG = 4,
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IGB_QUEUE_DEPLETED = 8,
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} queue_status;
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u32 txd_cmd;
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bus_dma_tag_t txtag;
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char mtx_name[16];
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#ifndef IGB_LEGACY_TX
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struct buf_ring *br;
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struct task txq_task;
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#endif
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u32 bytes; /* used for AIM */
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u32 packets;
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/* Soft Stats */
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unsigned long tso_tx;
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unsigned long no_tx_map_avail;
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unsigned long no_tx_dma_setup;
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u64 no_desc_avail;
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u64 total_packets;
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};
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/*
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* Receive ring: one per queue
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*/
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struct rx_ring {
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struct adapter *adapter;
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u32 me;
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struct igb_dma_alloc rxdma;
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union e1000_adv_rx_desc *rx_base;
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struct lro_ctrl lro;
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bool lro_enabled;
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bool hdr_split;
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struct mtx rx_mtx;
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char mtx_name[16];
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u32 next_to_refresh;
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u32 next_to_check;
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struct igb_rx_buf *rx_buffers;
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bus_dma_tag_t htag; /* dma tag for rx head */
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bus_dma_tag_t ptag; /* dma tag for rx packet */
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/*
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* First/last mbuf pointers, for
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* collecting multisegment RX packets.
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*/
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struct mbuf *fmp;
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struct mbuf *lmp;
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u32 bytes;
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u32 packets;
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int rdt;
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int rdh;
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/* Soft stats */
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u64 rx_split_packets;
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u64 rx_discarded;
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u64 rx_packets;
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u64 rx_bytes;
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};
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struct adapter {
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struct ifnet *ifp;
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struct e1000_hw hw;
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struct e1000_osdep osdep;
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struct device *dev;
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struct cdev *led_dev;
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struct resource *pci_mem;
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struct resource *msix_mem;
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int memrid;
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/*
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* Interrupt resources: this set is
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* either used for legacy, or for Link
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* when doing MSIX
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*/
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void *tag;
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struct resource *res;
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struct ifmedia media;
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struct callout timer;
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int msix;
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int if_flags;
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int pause_frames;
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struct mtx core_mtx;
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eventhandler_tag vlan_attach;
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eventhandler_tag vlan_detach;
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u16 num_vlans;
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u16 num_queues;
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/*
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** Shadow VFTA table, this is needed because
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** the real vlan filter table gets cleared during
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** a soft reset and the driver needs to be able
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** to repopulate it.
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*/
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u32 shadow_vfta[IGB_VFTA_SIZE];
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/* Info about the interface */
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u32 optics;
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u32 fc; /* local flow ctrl setting */
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int advertise; /* link speeds */
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bool link_active;
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u16 max_frame_size;
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u16 num_segs;
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u16 link_speed;
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bool link_up;
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u32 linkvec;
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u16 link_duplex;
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u32 dmac;
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int link_mask;
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/* Flags */
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u32 flags;
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/* Mbuf cluster size */
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u32 rx_mbuf_sz;
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/* Support for pluggable optics */
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bool sfp_probe;
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struct task link_task; /* Link tasklet */
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struct task mod_task; /* SFP tasklet */
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struct task msf_task; /* Multispeed Fiber */
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struct taskqueue *tq;
|
|
|
|
/*
|
|
** Queues:
|
|
** This is the irq holder, it has
|
|
** and RX/TX pair or rings associated
|
|
** with it.
|
|
*/
|
|
struct igb_queue *queues;
|
|
|
|
/*
|
|
* Transmit rings:
|
|
* Allocated at run time, an array of rings.
|
|
*/
|
|
struct tx_ring *tx_rings;
|
|
u32 num_tx_desc;
|
|
|
|
/*
|
|
* Receive rings:
|
|
* Allocated at run time, an array of rings.
|
|
*/
|
|
struct rx_ring *rx_rings;
|
|
u64 que_mask;
|
|
u32 num_rx_desc;
|
|
|
|
/* Multicast array memory */
|
|
u8 *mta;
|
|
|
|
/* Misc stats maintained by the driver */
|
|
unsigned long device_control;
|
|
unsigned long dropped_pkts;
|
|
unsigned long eint_mask;
|
|
unsigned long int_mask;
|
|
unsigned long link_irq;
|
|
unsigned long mbuf_defrag_failed;
|
|
unsigned long no_tx_dma_setup;
|
|
unsigned long packet_buf_alloc_rx;
|
|
unsigned long packet_buf_alloc_tx;
|
|
unsigned long rx_control;
|
|
unsigned long rx_overruns;
|
|
unsigned long watchdog_events;
|
|
|
|
/* Used in pf and vf */
|
|
void *stats;
|
|
|
|
int enable_aim;
|
|
int has_manage;
|
|
int wol;
|
|
int rx_process_limit;
|
|
int tx_process_limit;
|
|
u16 vf_ifp; /* a VF interface */
|
|
bool in_detach; /* Used only in igb_ioctl */
|
|
|
|
};
|
|
|
|
/* ******************************************************************************
|
|
* vendor_info_array
|
|
*
|
|
* This array contains the list of Subvendor/Subdevice IDs on which the driver
|
|
* should load.
|
|
*
|
|
* ******************************************************************************/
|
|
typedef struct _igb_vendor_info_t {
|
|
unsigned int vendor_id;
|
|
unsigned int device_id;
|
|
unsigned int subvendor_id;
|
|
unsigned int subdevice_id;
|
|
unsigned int index;
|
|
} igb_vendor_info_t;
|
|
|
|
struct igb_tx_buf {
|
|
union e1000_adv_tx_desc *eop;
|
|
struct mbuf *m_head;
|
|
bus_dmamap_t map;
|
|
};
|
|
|
|
struct igb_rx_buf {
|
|
struct mbuf *m_head;
|
|
struct mbuf *m_pack;
|
|
bus_dmamap_t hmap; /* bus_dma map for header */
|
|
bus_dmamap_t pmap; /* bus_dma map for packet */
|
|
};
|
|
|
|
/*
|
|
** Find the number of unrefreshed RX descriptors
|
|
*/
|
|
static inline u16
|
|
igb_rx_unrefreshed(struct rx_ring *rxr)
|
|
{
|
|
struct adapter *adapter = rxr->adapter;
|
|
|
|
if (rxr->next_to_check > rxr->next_to_refresh)
|
|
return (rxr->next_to_check - rxr->next_to_refresh - 1);
|
|
else
|
|
return ((adapter->num_rx_desc + rxr->next_to_check) -
|
|
rxr->next_to_refresh - 1);
|
|
}
|
|
|
|
#define IGB_CORE_LOCK_INIT(_sc, _name) \
|
|
mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF)
|
|
#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
|
|
#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
|
|
#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
|
|
#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
|
|
|
|
#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
|
|
#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
|
|
#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
|
|
#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
|
|
#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
|
|
|
|
#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
|
|
#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
|
|
#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
|
|
#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED)
|
|
|
|
#define UPDATE_VF_REG(reg, last, cur) \
|
|
{ \
|
|
u32 new = E1000_READ_REG(hw, reg); \
|
|
if (new < last) \
|
|
cur += 0x100000000LL; \
|
|
last = new; \
|
|
cur &= 0xFFFFFFFF00000000LL; \
|
|
cur |= new; \
|
|
}
|
|
|
|
#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504
|
|
static __inline int
|
|
drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br)
|
|
{
|
|
#ifdef ALTQ
|
|
if (ALTQ_IS_ENABLED(&ifp->if_snd))
|
|
return (1);
|
|
#endif
|
|
return (!buf_ring_empty(br));
|
|
}
|
|
#endif
|
|
|
|
#endif /* _IF_IGB_H_ */
|
|
|
|
|