43d0bd9696
"Revert revision 1.4. Intel CPUs with family 0x6, model 0xE and later (i.e., Intel Core(TM)) have a PMC architecture that differs somewhat from previous CPUs in family 0x6. Even though the basic programming model is similar, the documented set of legal values that may be loaded into their PMC MSRs differs from that of the previous PMCs in family 0x6 and reusing bit values legal for the older PMCs could result in undefined behaviour in the general case."
190 lines
4.5 KiB
C
190 lines
4.5 KiB
C
/*-
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* Copyright (c) 2005, Joseph Koshy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/pmc.h>
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#include <sys/systm.h>
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#include <machine/apicreg.h>
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#include <machine/pmc_mdep.h>
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#include <machine/md_var.h>
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extern volatile lapic_t *lapic;
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void
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pmc_x86_lapic_enable_pmc_interrupt(void)
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{
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uint32_t value;
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value = lapic->lvt_pcint;
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value &= ~APIC_LVT_M;
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lapic->lvt_pcint = value;
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}
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static struct pmc_mdep *
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pmc_intel_initialize(void)
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{
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struct pmc_mdep *pmc_mdep;
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enum pmc_cputype cputype;
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int error, model;
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KASSERT(strcmp(cpu_vendor, "GenuineIntel") == 0,
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("[intel,%d] Initializing non-intel processor", __LINE__));
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PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
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cputype = -1;
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switch (cpu_id & 0xF00) {
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#if defined(__i386__)
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case 0x500: /* Pentium family processors */
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cputype = PMC_CPU_INTEL_P5;
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break;
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case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
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switch ((cpu_id & 0xF0) >> 4) { /* model number field */
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case 0x1:
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cputype = PMC_CPU_INTEL_P6;
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break;
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case 0x3: case 0x5:
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cputype = PMC_CPU_INTEL_PII;
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break;
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case 0x6:
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cputype = PMC_CPU_INTEL_CL;
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break;
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case 0x7: case 0x8: case 0xA: case 0xB:
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cputype = PMC_CPU_INTEL_PIII;
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break;
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case 0x9: case 0xD:
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cputype = PMC_CPU_INTEL_PM;
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break;
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}
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break;
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#endif
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#if defined(__i386__) || defined(__amd64__)
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case 0xF00: /* P4 */
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model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
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if (model >= 0 && model <= 6) /* known models */
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cputype = PMC_CPU_INTEL_PIV;
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break;
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}
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#endif
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if ((int) cputype == -1) {
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printf("pmc: Unknown Intel CPU.\n");
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return NULL;
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}
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MALLOC(pmc_mdep, struct pmc_mdep *, sizeof(struct pmc_mdep),
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M_PMC, M_WAITOK|M_ZERO);
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pmc_mdep->pmd_cputype = cputype;
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pmc_mdep->pmd_nclass = 2;
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pmc_mdep->pmd_classes[0].pm_class = PMC_CLASS_TSC;
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pmc_mdep->pmd_classes[0].pm_caps = PMC_CAP_READ;
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pmc_mdep->pmd_classes[0].pm_width = 64;
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pmc_mdep->pmd_nclasspmcs[0] = 1;
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error = 0;
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switch (cputype) {
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#if defined(__i386__) || defined(__amd64__)
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/*
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* Intel Pentium 4 Processors, and P4/EMT64 processors.
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*/
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case PMC_CPU_INTEL_PIV:
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error = pmc_initialize_p4(pmc_mdep);
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break;
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#endif
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#if defined(__i386__)
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/*
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* P6 Family Processors
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*/
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case PMC_CPU_INTEL_P6:
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case PMC_CPU_INTEL_CL:
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case PMC_CPU_INTEL_PII:
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case PMC_CPU_INTEL_PIII:
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case PMC_CPU_INTEL_PM:
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error = pmc_initialize_p6(pmc_mdep);
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break;
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/*
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* Intel Pentium PMCs.
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*/
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case PMC_CPU_INTEL_P5:
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error = pmc_initialize_p5(pmc_mdep);
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break;
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#endif
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default:
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KASSERT(0,("[intel,%d] Unknown CPU type", __LINE__));
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}
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if (error) {
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FREE(pmc_mdep, M_PMC);
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pmc_mdep = NULL;
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}
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return pmc_mdep;
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}
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/*
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* Machine dependent initialization for x86 class platforms.
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*/
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struct pmc_mdep *
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pmc_md_initialize()
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{
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int i;
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struct pmc_mdep *md;
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/* determine the CPU kind */
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md = NULL;
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if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
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md = pmc_amd_initialize();
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else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
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md = pmc_intel_initialize();
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/* disallow sampling if we do not have an LAPIC */
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if (md != NULL && lapic == NULL)
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for (i = 1; i < md->pmd_nclass; i++)
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md->pmd_classes[i].pm_caps &= ~PMC_CAP_INTERRUPT;
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return md;
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}
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