80568041a3
static device mappings. This SoC relied heavily on the fact that all devices were static-mapped at a fixed address, and it (rather bogusly) used bus_space read and write calls passing hard-coded virtual addresses instead of proper bus handles, relying on the fact that the virtual addresses of the mappings were known at compile time, and relying on the implementation details of arm bus_space never changing. All such usage was replaced with calls to bus_space_map() to obtain a proper bus handle for the read/write calls. This required adjusting some of the #define values that map out hardware registers, and some of them were renamed in the process to make it clear which were defining absolute physical addresses and which were defining offsets. (The ones that just define offsets don't appear to be referenced and probably serve no value other than perhaps documentation.)
139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
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*/
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#include "opt_ddb.h"
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/devmap.h>
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#include <machine/machdep.h>
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#include <arm/lpc/lpcreg.h>
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#include <arm/lpc/lpcvar.h>
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#include <dev/fdt/fdt_common.h>
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vm_offset_t
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initarm_lastaddr(void)
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{
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return (arm_devmap_lastaddr());
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}
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void
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initarm_early_init(void)
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{
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}
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void
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initarm_gpio_init(void)
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{
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/*
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* Set initial values of GPIO output ports
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*/
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platform_gpio_init();
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}
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void
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initarm_late_init(void)
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{
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}
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/*
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* Add a single static device mapping.
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* The values used were taken from the ranges property of the SoC node in the
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* dts file when this code was converted to arm_devmap_add_entry().
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*/
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int
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initarm_devmap_init(void)
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{
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arm_devmap_add_entry(LPC_DEV_PHYS_BASE, LPC_DEV_SIZE);
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return (0);
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}
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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return (NULL);
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}
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int
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bus_dma_get_range_nb(void)
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{
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return (0);
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}
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void
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cpu_reset(void)
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{
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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bst = fdtbus_bs_tag;
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/* Enable WDT */
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bus_space_map(bst, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0, &bsh);
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bus_space_write_4(bst, bsh, LPC_CLKPWR_TIMCLK_CTRL,
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LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG);
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bus_space_unmap(bst, bsh, LPC_CLKPWR_SIZE);
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/* Instant assert of RESETOUT_N with pulse length 1ms */
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bus_space_map(bst, LPC_WDTIM_PHYS_BASE, LPC_WDTIM_SIZE, 0, &bsh);
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bus_space_write_4(bst, bsh, LPC_WDTIM_PULSE, 13000);
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bus_space_write_4(bst, bsh, LPC_WDTIM_MCTRL, 0x70);
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bus_space_unmap(bst, bsh, LPC_WDTIM_SIZE);
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for (;;)
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continue;
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}
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