ad6c99f277
Reapply r364240 after driver update in r365617. Reviewed by: lwhsu Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D27561
288 lines
12 KiB
C
288 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright (c) 2020, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef _ICE_COMMON_H_
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#define _ICE_COMMON_H_
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#include "ice_type.h"
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#include "ice_nvm.h"
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#include "ice_flex_pipe.h"
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#include "virtchnl.h"
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#include "ice_switch.h"
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enum ice_fw_modes {
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ICE_FW_MODE_NORMAL,
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ICE_FW_MODE_DBG,
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ICE_FW_MODE_REC,
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ICE_FW_MODE_ROLLBACK
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};
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void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq);
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bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq);
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enum ice_status ice_init_hw(struct ice_hw *hw);
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void ice_deinit_hw(struct ice_hw *hw);
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enum ice_status ice_check_reset(struct ice_hw *hw);
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enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
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enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
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enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
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void ice_shutdown_all_ctrlq(struct ice_hw *hw);
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void ice_destroy_all_ctrlq(struct ice_hw *hw);
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enum ice_status
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ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
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struct ice_rq_event_info *e, u16 *pending);
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enum ice_status
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ice_get_link_status(struct ice_port_info *pi, bool *link_up);
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enum ice_status ice_update_link_info(struct ice_port_info *pi);
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enum ice_status
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ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
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enum ice_aq_res_access_type access, u32 timeout);
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void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
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enum ice_status
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ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res);
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enum ice_status
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ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res);
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enum ice_status
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ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
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struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
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enum ice_adminq_opc opc, struct ice_sq_cd *cd);
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enum ice_status
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ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
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struct ice_aq_desc *desc, void *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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void ice_clear_pxe_mode(struct ice_hw *hw);
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enum ice_status ice_get_caps(struct ice_hw *hw);
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void ice_set_safe_mode_caps(struct ice_hw *hw);
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enum ice_status ice_set_mac_type(struct ice_hw *hw);
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/* Define a macro that will align a pointer to point to the next memory address
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* that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
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* example, given the variable pointer = 0x1006, then after the following call:
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*
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* pointer = ICE_ALIGN(pointer, 4)
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*
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* ... the value of pointer would equal 0x1008, since 0x1008 is the next
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* address after 0x1006 which is divisible by 4.
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*/
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#define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1))
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enum ice_status
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ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
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u32 rxq_index);
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enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);
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enum ice_status
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ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);
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enum ice_status
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ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
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struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
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u32 tx_cmpltnq_index);
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enum ice_status
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ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);
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enum ice_status
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ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
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struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
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u32 tx_drbell_q_index);
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enum ice_status
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ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
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u16 lut_size);
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enum ice_status
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ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
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u16 lut_size);
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enum ice_status
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ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
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struct ice_aqc_get_set_rss_keys *keys);
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enum ice_status
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ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
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struct ice_aqc_get_set_rss_keys *keys);
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enum ice_status
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ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
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struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
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bool is_tc_change, bool subseq_call, bool flush_pipe,
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u8 timeout, u32 *blocked_cgds,
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struct ice_aqc_move_txqs_data *buf, u16 buf_size,
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u8 *txqs_moved, struct ice_sq_cd *cd);
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bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
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enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
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void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
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extern const struct ice_ctx_ele ice_tlan_ctx_info[];
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enum ice_status
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ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
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const struct ice_ctx_ele *ce_info);
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enum ice_status
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ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
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void *buf, u16 buf_size, struct ice_sq_cd *cd);
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enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi,
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bool save_bad_pac, bool pad_short_pac, bool double_vlan,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
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struct ice_aqc_get_phy_caps_data *caps,
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struct ice_sq_cd *cd);
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void
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ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
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u16 link_speeds_bitmap);
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enum ice_status
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ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
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struct ice_sq_cd *cd);
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enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
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enum ice_status
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ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
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struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
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bool ice_fw_supports_link_override(struct ice_hw *hw);
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enum ice_status
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ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
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struct ice_port_info *pi);
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bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
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enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
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enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
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enum ice_status
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ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
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bool ena_auto_link_update);
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bool
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ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
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struct ice_aqc_set_phy_cfg_data *cfg);
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void
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ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
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struct ice_aqc_get_phy_caps_data *caps,
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struct ice_aqc_set_phy_cfg_data *cfg);
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enum ice_status
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ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
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enum ice_fec_mode fec);
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enum ice_status
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ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
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struct ice_link_status *link, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
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u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
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bool write, struct ice_sq_cd *cd);
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enum ice_status
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ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);
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enum ice_status
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__ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data);
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enum ice_status
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__ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data);
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enum ice_status
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ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
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u16 *q_handle, u16 *q_ids, u32 *q_teids,
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enum ice_disq_rst_src rst_src, u16 vmvf_num,
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struct ice_sq_cd *cd);
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enum ice_status
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ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
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u16 *max_lanqs);
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enum ice_status
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ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
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u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
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void ice_replay_post(struct ice_hw *hw);
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void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
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void ice_sched_replay_agg(struct ice_hw *hw);
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enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi);
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enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
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enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi);
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enum ice_status
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ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
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struct ice_q_ctx *
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ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
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void
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ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
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u64 *prev_stat, u64 *cur_stat);
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void
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ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
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u64 *prev_stat, u64 *cur_stat);
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void
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ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
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struct ice_eth_stats *cur_stats);
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enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
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void ice_print_rollback_msg(struct ice_hw *hw);
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enum ice_status
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ice_aq_alternate_write(struct ice_hw *hw, u32 reg_addr0, u32 reg_val0,
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u32 reg_addr1, u32 reg_val1);
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enum ice_status
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ice_aq_alternate_read(struct ice_hw *hw, u32 reg_addr0, u32 *reg_val0,
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u32 reg_addr1, u32 *reg_val1);
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enum ice_status
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ice_aq_alternate_write_done(struct ice_hw *hw, u8 bios_mode,
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bool *reset_needed);
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enum ice_status ice_aq_alternate_clear(struct ice_hw *hw);
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enum ice_status
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ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
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struct ice_aqc_txsched_elem_data *buf);
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enum ice_status
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ice_get_cur_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status);
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enum ice_status
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ice_get_dflt_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status);
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enum ice_status ice_get_netlist_ver_info(struct ice_hw *hw);
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enum ice_status
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ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
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enum ice_status
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ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
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#endif /* _ICE_COMMON_H_ */
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