6ce70ec7f9
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201 lines
8.5 KiB
C
201 lines
8.5 KiB
C
/* $NetBSD: lsi64854reg.h,v 1.6 2008/04/28 20:23:50 martin Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-NetBSD
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*
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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/*
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* LSI 64854 DMA engine. Contains three independent channels
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* designed to interface with (a) a NCR539X SCSI controller,
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* (b) a AM7990 Ethernet controller, (c) Parallel port hardware..
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*/
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/*
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* Register offsets to bus handle.
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*/
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#define L64854_REG_CSR 0 /* Control bits */
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#define L64854_REG_ADDR 4 /* DMA Address */
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#define L64854_REG_CNT 8 /* DMA count */
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#define L64854_REG_CNT_MASK 0x00ffffff /* only 24 bits */
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#define L64854_REG_ENBAR 12 /* ENET Base register */
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#define L64854_REG_TEST 12 /* SCSI Test register */
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#define L64854_REG_HCR 16 /* PP Hardware Configuration */
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#define L64854_REG_OCR 18 /* PP Operation Configuration */
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#define L64854_REG_DR 20 /* PP Data register */
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#define L64854_REG_TCR 21 /* PP Transfer Control */
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#define L64854_REG_OR 22 /* PP Output register */
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#define L64854_REG_IR 23 /* PP Input register */
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#define L64854_REG_ICR 24 /* PP Interrupt Control */
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/*
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* Control bits common to all three channels.
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*/
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#define L64854_INT_PEND 0x00000001 /* Interrupt pending */
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#define L64854_ERR_PEND 0x00000002 /* Error pending */
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#define L64854_DRAINING 0x0000000c /* FIFO draining */
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#define L64854_INT_EN 0x00000010 /* Interrupt enable */
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#define L64854_INVALIDATE 0x00000020 /* Invalidate FIFO */
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#define L64854_SLAVE_ERR 0x00000040 /* Slave access size error */
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#define L64854_RESET 0x00000080 /* Reset device */
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#define L64854_WRITE 0x00000100 /* 1: xfer to memory */
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#define L64854_EN_DMA 0x00000200 /* enable DMA transfers */
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#define L64854_BURST_SIZE 0x000c0000 /* Read/write burst size */
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#define L64854_BURST_0 0x00080000 /* no bursts (SCSI-only) */
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#define L64854_BURST_16 0x00000000 /* 16-byte bursts */
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#define L64854_BURST_32 0x00040000 /* 32-byte bursts */
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#define L64854_BURST_64 0x000c0000 /* 64-byte bursts (fas) */
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#define L64854_RST_FAS366 0x08000000 /* FAS366 hardware reset */
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#define L64854_DEVID 0xf0000000 /* device ID bits */
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/*
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* SCSI DMA control bits.
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*/
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#define D_INT_PEND L64854_INT_PEND /* interrupt pending */
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#define D_ERR_PEND L64854_ERR_PEND /* error pending */
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#define D_DRAINING L64854_DRAINING /* fifo draining */
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#define D_INT_EN L64854_INT_EN /* interrupt enable */
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#define D_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
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#define D_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
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#define D_RESET L64854_RESET /* reset scsi */
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#define D_WRITE L64854_WRITE /* 1 = dev -> mem */
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#define D_EN_DMA L64854_EN_DMA /* enable DMA requests */
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#define D_EN_CNT 0x00002000 /* enable byte counter */
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#define D_TC 0x00004000 /* terminal count */
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#define D_WIDE_EN 0x00008000 /* enable wide mode SBUS DMA (fas) */
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#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */
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#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */
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#define D_DIAG 0x00100000 /* disable fifo drain on addr */
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#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */
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#define D_FASTER 0x00400000 /* 3 clocks per transfer */
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#define D_TCI_DIS 0x00800000 /* disable intr on D_TC */
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#define D_EN_NEXT 0x01000000 /* enable auto next address */
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#define D_DMA_ON 0x02000000 /* enable dma from scsi XXX */
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#define D_DSBL_PARITY_CHK \
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0x02000000 /* disable checking for parity on bus (default 1:fas) */
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#define D_A_LOADED 0x04000000 /* address loaded */
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#define D_NA_LOADED 0x08000000 /* next address loaded */
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#define D_HW_RESET_FAS366 \
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0x08000000 /* hardware reset FAS366 (fas) */
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#define D_DEV_ID L64854_DEVID /* device ID */
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#define DMAREV_0 0x00000000 /* Sunray DMA */
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#define DMAREV_ESC 0x40000000 /* DMA ESC array */
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#define DMAREV_1 0x80000000 /* 'DMA' */
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#define DMAREV_PLUS 0x90000000 /* 'DMA+' */
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#define DMAREV_2 0xa0000000 /* 'DMA2' */
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#define DMAREV_HME 0xb0000000 /* 'HME' */
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/*
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* revisions 0,1 and ESC have different bits.
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*/
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#define D_ESC_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */
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#define D_ESC_R_PEND 0x00000400 /* rev0,1: request pending */
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#define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */
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#define D_ESC_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */
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#define DDMACSR_BITS "\177\020" \
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"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
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"b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \
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"b\15ENCNT\0b\16TC\0\b\20DSBL_CSR_DRN\0" \
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"b\21DSBL_SCSI_DRN\0f\22\2BURST\0b\25TWOCYCLE\0" \
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"b\26FASTER\0b\27TCIDIS\0b\30ENNXT\0b\031DMAON\0" \
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"b\32ALOADED\0b\33NALOADED\0"
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/*
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* ENET DMA control bits.
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*/
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#define E_INT_PEND L64854_INT_PEND /* interrupt pending */
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#define E_ERR_PEND L64854_ERR_PEND /* error pending */
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#define E_DRAINING L64854_DRAINING /* fifo draining */
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#define E_INT_EN L64854_INT_EN /* interrupt enable */
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#define E_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
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#define E_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
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#define E_RESET L64854_RESET /* reset ENET */
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#define E_reserved1 0x00000300 /* */
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#define E_DRAIN 0x00000400 /* force Ecache drain */
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#define E_DSBL_WR_DRN 0x00000800 /* disable Ecache drain on .. */
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#define E_DSBL_RD_DRN 0x00001000 /* disable Ecache drain on .. */
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#define E_reserved2 0x00006000 /* */
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#define E_ILACC 0x00008000 /* ... */
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#define E_DSBL_BUF_WR 0x00010000 /* no buffering of slave writes */
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#define E_DSBL_WR_INVAL 0x00020000 /* no Ecache invalidate on slave writes */
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#define E_reserved3 0x00100000 /* */
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#define E_LOOP_TEST 0x00200000 /* loopback mode */
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#define E_TP_AUI 0x00400000 /* 1 for TP, 0 for AUI */
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#define E_reserved4 0x0c800000 /* */
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#define E_DEV_ID L64854_DEVID /* ID bits */
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#define EDMACSR_BITS "\177\020" \
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"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
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"b\06SLVERR\0b\07RST\0b\10WRITE\0b\12DRAIN\0" \
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"b\13DSBL_WR_DRN\0b\14DSBL_RD_DRN\0b\17ILACC\0" \
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"b\20DSBL_BUF_WR\0b\21DSBL_WR_INVAL\0" \
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"b\25LOOPTEST\0b\26TP\0"
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/*
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* PP DMA control bits.
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*/
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#define P_INT_PEND L64854_INT_PEND /* interrupt pending */
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#define P_ERR_PEND L64854_ERR_PEND /* error pending */
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#define P_DRAINING L64854_DRAINING /* fifo draining */
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#define P_INT_EN L64854_INT_EN /* interrupt enable */
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#define P_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
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#define P_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
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#define P_RESET L64854_RESET /* reset PP */
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#define P_WRITE L64854_WRITE /* 1: xfer to memory */
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#define P_EN_DMA L64854_EN_DMA /* enable DMA transfers */
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#define P_reserved1 0x00001c00 /* */
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#define P_EN_CNT 0x00002000 /* enable counter */
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#define P_TC 0x00004000 /* terminal count */
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#define P_reserved2 0x00038000 /* */
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#define P_DIAG 0x00100000 /* ... */
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#define P_reserved3 0x00600000 /* */
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#define P_TCI_DIS 0x00800000 /* no interrupt on terminal count */
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#define P_EN_NEXT 0x01000000 /* enable DMA chaining */
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#define P_DMA_ON 0x02000000 /* DMA xfers enabled */
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#define P_A_LOADED 0x04000000 /* addr and byte count valid */
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#define P_NA_LOADED 0x08000000 /* next addr & count valid but not used */
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#define P_DEV_ID L64854_DEVID /* ID bits */
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#define PDMACSR_BITS "\177\020" \
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"b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \
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"b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \
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"b\15ENCNT\0b\16TC\0\b\24DIAG\0b\27TCIDIS\0" \
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"b\30ENNXT\0b\031DMAON\0b\32ALOADED\0b\33NALOADED\0"
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