7e76048a69
can run on processors that don't have a FPU. This is typically the case for Book E processors. While a tuned system will probably want to use soft-float (or use a processor that has a FPU if the usage is FP intensive enough), allowing hard-float on FPU-less systems gives great portability and flexibility. Obtained from: NetBSD
153 lines
5.7 KiB
C
153 lines
5.7 KiB
C
/* $NetBSD: fpu_arith.h,v 1.4 2005/12/24 20:07:28 perry Exp $ */
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/* $FreeBSD$ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fpu_arith.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Extended-precision arithmetic.
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*
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* We hold the notion of a `carry register', which may or may not be a
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* machine carry bit or register. On the SPARC, it is just the machine's
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* carry bit.
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*
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* In the worst case, you can compute the carry from x+y as
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* (unsigned)(x + y) < (unsigned)x
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* and from x+y+c as
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* ((unsigned)(x + y + c) <= (unsigned)x && (y|c) != 0)
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* for example.
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*/
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#ifndef FPE_USE_ASM
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/* set up for extended-precision arithemtic */
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#define FPU_DECL_CARRY quad_t fpu_carry, fpu_tmp;
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/*
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* We have three kinds of add:
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* add with carry: r = x + y + c
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* add (ignoring current carry) and set carry: c'r = x + y + 0
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* add with carry and set carry: c'r = x + y + c
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* The macros use `C' for `use carry' and `S' for `set carry'.
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* Note that the state of the carry is undefined after ADDC and SUBC,
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* so if all you have for these is `add with carry and set carry',
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* that is OK.
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*
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* The same goes for subtract, except that we compute x - y - c.
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*
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* Finally, we have a way to get the carry into a `regular' variable,
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* or set it from a value. SET_CARRY turns 0 into no-carry, nonzero
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* into carry; GET_CARRY sets its argument to 0 or 1.
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*/
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#define FPU_ADDC(r, x, y) \
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(r) = (x) + (y) + (!!fpu_carry)
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#define FPU_ADDS(r, x, y) \
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{ \
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fpu_tmp = (quad_t)(x) + (quad_t)(y); \
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(r) = (u_int)fpu_tmp; \
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fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
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}
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#define FPU_ADDCS(r, x, y) \
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{ \
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fpu_tmp = (quad_t)(x) + (quad_t)(y) + (!!fpu_carry); \
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(r) = (u_int)fpu_tmp; \
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fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
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}
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#define FPU_SUBC(r, x, y) \
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(r) = (x) - (y) - (!!fpu_carry)
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#define FPU_SUBS(r, x, y) \
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{ \
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fpu_tmp = (quad_t)(x) - (quad_t)(y); \
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(r) = (u_int)fpu_tmp; \
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fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
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}
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#define FPU_SUBCS(r, x, y) \
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{ \
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fpu_tmp = (quad_t)(x) - (quad_t)(y) - (!!fpu_carry); \
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(r) = (u_int)fpu_tmp; \
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fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
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}
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#define FPU_GET_CARRY(r) (r) = (!!fpu_carry)
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#define FPU_SET_CARRY(v) fpu_carry = ((v) != 0)
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#else
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/* set up for extended-precision arithemtic */
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#define FPU_DECL_CARRY
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/*
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* We have three kinds of add:
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* add with carry: r = x + y + c
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* add (ignoring current carry) and set carry: c'r = x + y + 0
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* add with carry and set carry: c'r = x + y + c
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* The macros use `C' for `use carry' and `S' for `set carry'.
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* Note that the state of the carry is undefined after ADDC and SUBC,
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* so if all you have for these is `add with carry and set carry',
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* that is OK.
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*
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* The same goes for subtract, except that we compute x - y - c.
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*
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* Finally, we have a way to get the carry into a `regular' variable,
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* or set it from a value. SET_CARRY turns 0 into no-carry, nonzero
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* into carry; GET_CARRY sets its argument to 0 or 1.
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*/
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#define FPU_ADDC(r, x, y) \
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__asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
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#define FPU_ADDS(r, x, y) \
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__asm volatile("addc %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
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#define FPU_ADDCS(r, x, y) \
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__asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
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#define FPU_SUBC(r, x, y) \
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__asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
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#define FPU_SUBS(r, x, y) \
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__asm volatile("subfc %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
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#define FPU_SUBCS(r, x, y) \
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__asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
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#define FPU_GET_CARRY(r) __asm volatile("li %0,0; addie %0,%0,0" : "=r"(r))
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/* This one needs to destroy a temp register. */
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#define FPU_SET_CARRY(v) do { int __tmp; \
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__asm volatile("addic %0,%0,-1" : "r"(__tmp) : "r"(v)); \
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} while (0)
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#define FPU_SHL1_BY_ADD /* shift left 1 faster by ADDC than (a<<1)|(b>>31) */
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#endif
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