209 lines
5.6 KiB
C
209 lines
5.6 KiB
C
/*
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* Copyright (c) 2013-2016 Qlogic Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* File: ql_ioctl.h
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* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
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*/
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#ifndef _QL_IOCTL_H_
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#define _QL_IOCTL_H_
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#include <sys/ioccom.h>
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struct qla_reg_val {
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uint16_t rd;
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uint16_t direct;
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uint32_t reg;
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uint32_t val;
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};
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typedef struct qla_reg_val qla_reg_val_t;
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struct qla_rd_flash {
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uint32_t off;
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uint32_t data;
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};
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typedef struct qla_rd_flash qla_rd_flash_t;
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struct qla_wr_flash {
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uint32_t off;
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uint32_t size;
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void *buffer;
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uint32_t pattern;
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};
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typedef struct qla_wr_flash qla_wr_flash_t;
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struct qla_erase_flash {
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uint32_t off;
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uint32_t size;
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};
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typedef struct qla_erase_flash qla_erase_flash_t;
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struct qla_rd_pci_ids {
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uint16_t ven_id;
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uint16_t dev_id;
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uint16_t subsys_ven_id;
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uint16_t subsys_dev_id;
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uint8_t rev_id;
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};
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typedef struct qla_rd_pci_ids qla_rd_pci_ids_t;
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/*
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* structure encapsulating the value to read/write from/to offchip (MS) memory
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*/
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struct qla_offchip_mem_val {
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uint16_t rd;
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uint64_t off;
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uint32_t data_lo;
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uint32_t data_hi;
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uint32_t data_ulo;
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uint32_t data_uhi;
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};
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typedef struct qla_offchip_mem_val qla_offchip_mem_val_t;
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struct qla_rd_fw_dump {
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uint16_t pci_func;
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uint32_t minidump_size;
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void *minidump;
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};
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typedef struct qla_rd_fw_dump qla_rd_fw_dump_t;
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struct qla_drvr_state_tx {
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uint64_t base_p_addr;
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uint64_t cons_p_addr;
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uint32_t tx_prod_reg;
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uint32_t tx_cntxt_id;
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uint32_t txr_free;
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uint32_t txr_next;
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uint32_t txr_comp;
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};
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typedef struct qla_drvr_state_tx qla_drvr_state_tx_t;
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struct qla_drvr_state_sds {
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uint32_t sdsr_next; /* next entry in SDS ring to process */
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uint32_t sds_consumer;
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};
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typedef struct qla_drvr_state_sds qla_drvr_state_sds_t;
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struct qla_drvr_state_rx {
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uint32_t prod_std;
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uint32_t rx_next; /* next standard rcv ring to arm fw */;
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};
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typedef struct qla_drvr_state_rx qla_drvr_state_rx_t;
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struct qla_drvr_state_hdr {
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uint32_t drvr_version_major;
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uint32_t drvr_version_minor;
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uint32_t drvr_version_build;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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uint16_t link_speed;
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uint16_t cable_length;
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uint32_t cable_oui;
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uint8_t link_up;
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uint8_t module_type;
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uint8_t link_faults;
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uint32_t rcv_intr_coalesce;
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uint32_t xmt_intr_coalesce;
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uint32_t tx_state_offset;/* size = sizeof (qla_drvr_state_tx_t) * num_tx_rings */
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uint32_t rx_state_offset;/* size = sizeof (qla_drvr_state_rx_t) * num_rx_rings */
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uint32_t sds_state_offset;/* size = sizeof (qla_drvr_state_sds_t) * num_sds_rings */
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uint32_t num_tx_rings; /* number of tx rings */
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uint32_t txr_size; /* size of each tx ring in bytes */
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uint32_t txr_entries; /* number of descriptors in each tx ring */
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uint32_t txr_offset; /* start of tx ring [0 - #rings] content */
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uint32_t num_rx_rings; /* number of rx rings */
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uint32_t rxr_size; /* size of each rx ring in bytes */
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uint32_t rxr_entries; /* number of descriptors in each rx ring */
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uint32_t rxr_offset; /* start of rx ring [0 - #rings] content */
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uint32_t num_sds_rings; /* number of sds rings */
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uint32_t sds_ring_size; /* size of each sds ring in bytes */
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uint32_t sds_entries; /* number of descriptors in each sds ring */
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uint32_t sds_offset; /* start of sds ring [0 - #rings] content */
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};
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typedef struct qla_drvr_state_hdr qla_drvr_state_hdr_t;
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struct qla_driver_state {
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uint32_t size;
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void *buffer;
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};
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typedef struct qla_driver_state qla_driver_state_t;
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/*
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* Read/Write Register
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*/
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#define QLA_RDWR_REG _IOWR('q', 1, qla_reg_val_t)
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/*
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* Read Flash
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*/
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#define QLA_RD_FLASH _IOWR('q', 2, qla_rd_flash_t)
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/*
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* Write Flash
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*/
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#define QLA_WR_FLASH _IOWR('q', 3, qla_wr_flash_t)
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/*
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* Read Offchip (MS) Memory
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*/
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#define QLA_RDWR_MS_MEM _IOWR('q', 4, qla_offchip_mem_val_t)
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/*
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* Erase Flash
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*/
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#define QLA_ERASE_FLASH _IOWR('q', 5, qla_erase_flash_t)
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/*
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* Read PCI IDs
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*/
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#define QLA_RD_PCI_IDS _IOWR('q', 6, qla_rd_pci_ids_t)
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/*
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* Read Minidump Template Size
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*/
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#define QLA_RD_FW_DUMP_SIZE _IOWR('q', 7, qla_rd_fw_dump_t)
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/*
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* Read Minidump Template
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*/
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#define QLA_RD_FW_DUMP _IOWR('q', 8, qla_rd_fw_dump_t)
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/*
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* Read Driver State
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*/
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#define QLA_RD_DRVR_STATE _IOWR('q', 9, qla_driver_state_t)
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#endif /* #ifndef _QL_IOCTL_H_ */
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