9bf4c9c1b0
- Add 3 new functions to the pci_if interface along with suitable wrappers
to provide the device driver visible API:
- pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count'
here is an in and out parameter. The driver stores the desired number
of messages in '*count' before calling the function. On success,
'*count' holds the number of messages allocated to the device. Also on
success, the driver can access the messages as SYS_RES_IRQ resources
starting at rid 1. Note that the legacy INTx interrupt resource will
not be available when using MSI. Note that this function will allocate
either MSI or MSI-X messages depending on the devices capabilities and
the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note
that the driver should activate the memory resource that holds the
MSI-X table and pending bit array (PBA) before calling this function
if the device supports MSI-X.
- pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function
releases the messages allocated for this device. All of the
SYS_RES_IRQ resources need to be released for this function to succeed.
- pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns
the maximum number of MSI or MSI-X messages supported by this device.
MSI-X is preferred if present, but this function will honor the
'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function
should return the largest value that pci_alloc_msi() can return
(assuming the MD code is able to allocate sufficient backing resources
for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
PCI bus driver. (The various other PCI bus drivers such as for ACPI and
OFW will inherit these default implementations.) This default
implementation depends on 4 new pcib_if methods that bubble up through
the PCI bridges to the MD code to allocate IRQ values and perform any
needed MD setup code needed:
- PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
- PCIB_RELEASE_MSI() releases a group of MSI messages.
- PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
- PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
request up to the parent bus's parent bridge driver and use the
default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
interrupts:
- pci_enable_msi(dev, address, data) programs the MSI capability address
and data registers for a group of MSI messages
- pci_enable_msix(dev, index, address, data) initializes a single MSI-X
message in the MSI-X table
- pci_mask_msix(dev, index) masks a single MSI-X message
- pci_unmask_msix(dev, index) unmasks a single MSI-X message
- pci_pending_msix(dev, index) returns true if the specified MSI-X
message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
block in a PCI devices ivars and restore the values when a device is
resumed. Note that the MSI-X table is not currently restored during
resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
across in the pci_cfgreg block in the ivars for PCI devices.
Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by: scottl, grehan, jfv
MFC after: 2 months
672 lines
18 KiB
C
672 lines
18 KiB
C
/*-
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* Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
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* Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* PCI:PCI bridge support.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/resource.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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static int pcib_probe(device_t dev);
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static device_method_t pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pcib_probe),
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DEVMETHOD(device_attach, pcib_attach),
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DEVMETHOD(device_detach, bus_generic_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, pcib_read_ivar),
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DEVMETHOD(bus_write_ivar, pcib_write_ivar),
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DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, pcib_maxslots),
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DEVMETHOD(pcib_read_config, pcib_read_config),
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DEVMETHOD(pcib_write_config, pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
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DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
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DEVMETHOD(pcib_release_msi, pcib_release_msi),
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DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
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DEVMETHOD(pcib_release_msix, pcib_release_msix),
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{ 0, 0 }
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};
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static devclass_t pcib_devclass;
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DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
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DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
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/*
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* Is the prefetch window open (eg, can we allocate memory in it?)
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*/
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static int
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pcib_is_prefetch_open(struct pcib_softc *sc)
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{
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return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
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}
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/*
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* Is the nonprefetch window open (eg, can we allocate memory in it?)
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*/
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static int
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pcib_is_nonprefetch_open(struct pcib_softc *sc)
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{
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return (sc->membase > 0 && sc->membase < sc->memlimit);
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}
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/*
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* Is the io window open (eg, can we allocate ports in it?)
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*/
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static int
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pcib_is_io_open(struct pcib_softc *sc)
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{
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return (sc->iobase > 0 && sc->iobase < sc->iolimit);
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}
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/*
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* Generic device interface
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*/
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static int
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pcib_probe(device_t dev)
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{
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if ((pci_get_class(dev) == PCIC_BRIDGE) &&
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(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
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device_set_desc(dev, "PCI-PCI bridge");
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return(-10000);
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}
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return(ENXIO);
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}
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void
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pcib_attach_common(device_t dev)
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{
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struct pcib_softc *sc;
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uint8_t iolow;
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sc = device_get_softc(dev);
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sc->dev = dev;
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/*
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* Get current bridge configuration.
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*/
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sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
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sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
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sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
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sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
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sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
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sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
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/*
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* Determine current I/O decode.
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*/
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if (sc->command & PCIM_CMD_PORTEN) {
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iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
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if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
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sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
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pci_read_config(dev, PCIR_IOBASEL_1, 1));
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} else {
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sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
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}
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iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
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if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
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sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
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pci_read_config(dev, PCIR_IOLIMITL_1, 1));
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} else {
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sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
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}
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}
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/*
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* Determine current memory decode.
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*/
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if (sc->command & PCIM_CMD_MEMEN) {
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sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
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sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
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sc->pmembase = PCI_PPBMEMBASE(pci_read_config(dev, PCIR_PMBASEH_1, 4),
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pci_read_config(dev, PCIR_PMBASEL_1, 2));
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sc->pmemlimit = PCI_PPBMEMLIMIT(pci_read_config(dev, PCIR_PMLIMITH_1, 4),
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pci_read_config(dev, PCIR_PMLIMITL_1, 2));
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}
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/*
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* Quirk handling.
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*/
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switch (pci_get_devid(dev)) {
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case 0x12258086: /* Intel 82454KX/GX (Orion) */
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{
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uint8_t supbus;
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supbus = pci_read_config(dev, 0x41, 1);
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if (supbus != 0xff) {
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sc->secbus = supbus + 1;
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sc->subbus = supbus + 1;
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}
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break;
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}
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/*
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* The i82380FB mobile docking controller is a PCI-PCI bridge,
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* and it is a subtractive bridge. However, the ProgIf is wrong
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* so the normal setting of PCIB_SUBTRACTIVE bit doesn't
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* happen. There's also a Toshiba bridge that behaves this
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* way.
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*/
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case 0x124b8086: /* Intel 82380FB Mobile */
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case 0x060513d7: /* Toshiba ???? */
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sc->flags |= PCIB_SUBTRACTIVE;
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break;
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/* Compaq R3000 BIOS sets wrong subordinate bus number. */
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case 0x00dd10de:
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{
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char *cp;
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if ((cp = getenv("smbios.planar.maker")) == NULL)
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break;
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if (strncmp(cp, "Compal", 6) != 0) {
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freeenv(cp);
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break;
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}
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freeenv(cp);
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if ((cp = getenv("smbios.planar.product")) == NULL)
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break;
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if (strncmp(cp, "08A0", 4) != 0) {
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freeenv(cp);
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break;
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}
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freeenv(cp);
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if (sc->subbus < 0xa) {
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pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
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sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
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}
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break;
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}
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}
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/*
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* Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
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* but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
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* BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
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* This means they act as if they were subtractively decoding
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* bridges and pass all transactions. Mark them and real ProgIf 1
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* parts as subtractive.
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*/
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if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
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pci_read_config(dev, PCIR_PROGIF, 1) == 1)
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sc->flags |= PCIB_SUBTRACTIVE;
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if (bootverbose) {
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device_printf(dev, " secondary bus %d\n", sc->secbus);
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device_printf(dev, " subordinate bus %d\n", sc->subbus);
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device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
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if (pcib_is_nonprefetch_open(sc))
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device_printf(dev, " memory decode 0x%jx-0x%jx\n",
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(uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
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if (pcib_is_prefetch_open(sc))
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device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
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(uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
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else
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device_printf(dev, " no prefetched decode\n");
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if (sc->flags & PCIB_SUBTRACTIVE)
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device_printf(dev, " Subtractively decoded bridge.\n");
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}
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/*
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* XXX If the secondary bus number is zero, we should assign a bus number
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* since the BIOS hasn't, then initialise the bridge.
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*/
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/*
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* XXX If the subordinate bus number is less than the secondary bus number,
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* we should pick a better value. One sensible alternative would be to
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* pick 255; the only tradeoff here is that configuration transactions
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* would be more widely routed than absolutely necessary.
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*/
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}
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int
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pcib_attach(device_t dev)
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{
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struct pcib_softc *sc;
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device_t child;
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pcib_attach_common(dev);
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sc = device_get_softc(dev);
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if (sc->secbus != 0) {
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child = device_add_child(dev, "pci", sc->secbus);
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if (child != NULL)
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return(bus_generic_attach(dev));
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}
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/* no secondary bus; we should have fixed this */
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return(0);
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}
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int
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pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct pcib_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = sc->secbus;
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return(0);
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}
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return(ENOENT);
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}
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int
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pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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{
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struct pcib_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->secbus = value;
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break;
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}
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return(ENOENT);
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}
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/*
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* We have to trap resource allocation requests and ensure that the bridge
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* is set up to, or capable of handling them.
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*/
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struct resource *
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pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct pcib_softc *sc = device_get_softc(dev);
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const char *name, *suffix;
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int ok;
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/*
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* Fail the allocation for this range if it's not supported.
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*/
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name = device_get_nameunit(child);
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if (name == NULL) {
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name = "";
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suffix = "";
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} else
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suffix = " ";
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switch (type) {
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case SYS_RES_IOPORT:
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ok = 0;
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if (!pcib_is_io_open(sc))
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break;
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ok = (start >= sc->iobase && end <= sc->iolimit);
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/*
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* Make sure we allow access to VGA I/O addresses when the
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* bridge has the "VGA Enable" bit set.
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*/
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if (!ok && pci_is_vga_ioport_range(start, end))
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ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
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if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
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if (!ok) {
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if (start < sc->iobase)
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start = sc->iobase;
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if (end > sc->iolimit)
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end = sc->iolimit;
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if (start < end)
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ok = 1;
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}
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} else {
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ok = 1;
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#if 1
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if (start < sc->iobase && end > sc->iolimit) {
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start = sc->iobase;
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end = sc->iolimit;
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}
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#endif
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}
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if (end < start) {
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device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
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end, start);
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start = 0;
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end = 0;
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ok = 0;
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}
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if (!ok) {
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device_printf(dev, "%s%srequested unsupported I/O "
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"range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
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name, suffix, start, end, sc->iobase, sc->iolimit);
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return (NULL);
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}
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if (bootverbose)
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device_printf(dev,
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"%s%srequested I/O range 0x%lx-0x%lx: in range\n",
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name, suffix, start, end);
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break;
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case SYS_RES_MEMORY:
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ok = 0;
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if (pcib_is_nonprefetch_open(sc))
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ok = ok || (start >= sc->membase && end <= sc->memlimit);
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if (pcib_is_prefetch_open(sc))
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ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
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/*
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* Make sure we allow access to VGA memory addresses when the
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* bridge has the "VGA Enable" bit set.
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*/
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if (!ok && pci_is_vga_memory_range(start, end))
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ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
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if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
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if (!ok) {
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ok = 1;
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if (flags & RF_PREFETCHABLE) {
|
|
if (pcib_is_prefetch_open(sc)) {
|
|
if (start < sc->pmembase)
|
|
start = sc->pmembase;
|
|
if (end > sc->pmemlimit)
|
|
end = sc->pmemlimit;
|
|
} else {
|
|
ok = 0;
|
|
}
|
|
} else { /* non-prefetchable */
|
|
if (pcib_is_nonprefetch_open(sc)) {
|
|
if (start < sc->membase)
|
|
start = sc->membase;
|
|
if (end > sc->memlimit)
|
|
end = sc->memlimit;
|
|
} else {
|
|
ok = 0;
|
|
}
|
|
}
|
|
}
|
|
} else if (!ok) {
|
|
ok = 1; /* subtractive bridge: always ok */
|
|
#if 1
|
|
if (pcib_is_nonprefetch_open(sc)) {
|
|
if (start < sc->membase && end > sc->memlimit) {
|
|
start = sc->membase;
|
|
end = sc->memlimit;
|
|
}
|
|
}
|
|
if (pcib_is_prefetch_open(sc)) {
|
|
if (start < sc->pmembase && end > sc->pmemlimit) {
|
|
start = sc->pmembase;
|
|
end = sc->pmemlimit;
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
if (end < start) {
|
|
device_printf(dev, "memory: end (%lx) < start (%lx)\n",
|
|
end, start);
|
|
start = 0;
|
|
end = 0;
|
|
ok = 0;
|
|
}
|
|
if (!ok && bootverbose)
|
|
device_printf(dev,
|
|
"%s%srequested unsupported memory range %#lx-%#lx "
|
|
"(decoding %#jx-%#jx, %#jx-%#jx)\n",
|
|
name, suffix, start, end,
|
|
(uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
|
|
(uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
|
|
if (!ok)
|
|
return (NULL);
|
|
if (bootverbose)
|
|
device_printf(dev,"%s%srequested memory range "
|
|
"0x%lx-0x%lx: good\n",
|
|
name, suffix, start, end);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
/*
|
|
* Bridge is OK decoding this resource, so pass it up.
|
|
*/
|
|
return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
|
|
count, flags));
|
|
}
|
|
|
|
/*
|
|
* PCIB interface.
|
|
*/
|
|
int
|
|
pcib_maxslots(device_t dev)
|
|
{
|
|
return(PCI_SLOTMAX);
|
|
}
|
|
|
|
/*
|
|
* Since we are a child of a PCI bus, its parent must support the pcib interface.
|
|
*/
|
|
uint32_t
|
|
pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
|
|
{
|
|
return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
|
|
}
|
|
|
|
void
|
|
pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
|
|
{
|
|
PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
|
|
}
|
|
|
|
/*
|
|
* Route an interrupt across a PCI bridge.
|
|
*/
|
|
int
|
|
pcib_route_interrupt(device_t pcib, device_t dev, int pin)
|
|
{
|
|
device_t bus;
|
|
int parent_intpin;
|
|
int intnum;
|
|
|
|
/*
|
|
*
|
|
* The PCI standard defines a swizzle of the child-side device/intpin to
|
|
* the parent-side intpin as follows.
|
|
*
|
|
* device = device on child bus
|
|
* child_intpin = intpin on child bus slot (0-3)
|
|
* parent_intpin = intpin on parent bus slot (0-3)
|
|
*
|
|
* parent_intpin = (device + child_intpin) % 4
|
|
*/
|
|
parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
|
|
|
|
/*
|
|
* Our parent is a PCI bus. Its parent must export the pcib interface
|
|
* which includes the ability to route interrupts.
|
|
*/
|
|
bus = device_get_parent(pcib);
|
|
intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
|
|
if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
|
|
device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
|
|
pci_get_slot(dev), 'A' + pin - 1, intnum);
|
|
}
|
|
return(intnum);
|
|
}
|
|
|
|
/* Pass request to alloc MSI messages up to the parent bridge. */
|
|
int
|
|
pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
|
|
{
|
|
device_t bus;
|
|
|
|
bus = device_get_parent(pcib);
|
|
return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
|
|
irqs));
|
|
}
|
|
|
|
/* Pass request to release MSI messages up to the parent bridge. */
|
|
int
|
|
pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
|
|
{
|
|
device_t bus;
|
|
|
|
bus = device_get_parent(pcib);
|
|
return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
|
|
}
|
|
|
|
/* Pass request to alloc an MSI-X message up to the parent bridge. */
|
|
int
|
|
pcib_alloc_msix(device_t pcib, device_t dev, int index, int *irq)
|
|
{
|
|
device_t bus;
|
|
|
|
bus = device_get_parent(pcib);
|
|
return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, index, irq));
|
|
}
|
|
|
|
/* Pass request to release an MSI-X message up to the parent bridge. */
|
|
int
|
|
pcib_release_msix(device_t pcib, device_t dev, int irq)
|
|
{
|
|
device_t bus;
|
|
|
|
bus = device_get_parent(pcib);
|
|
return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
|
|
}
|
|
|
|
/*
|
|
* Try to read the bus number of a host-PCI bridge using appropriate config
|
|
* registers.
|
|
*/
|
|
int
|
|
host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
|
|
uint8_t *busnum)
|
|
{
|
|
uint32_t id;
|
|
|
|
id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
|
|
if (id == 0xffffffff)
|
|
return (0);
|
|
|
|
switch (id) {
|
|
case 0x12258086:
|
|
/* Intel 824?? */
|
|
/* XXX This is a guess */
|
|
/* *busnum = read_config(bus, slot, func, 0x41, 1); */
|
|
*busnum = bus;
|
|
break;
|
|
case 0x84c48086:
|
|
/* Intel 82454KX/GX (Orion) */
|
|
*busnum = read_config(bus, slot, func, 0x4a, 1);
|
|
break;
|
|
case 0x84ca8086:
|
|
/*
|
|
* For the 450nx chipset, there is a whole bundle of
|
|
* things pretending to be host bridges. The MIOC will
|
|
* be seen first and isn't really a pci bridge (the
|
|
* actual busses are attached to the PXB's). We need to
|
|
* read the registers of the MIOC to figure out the
|
|
* bus numbers for the PXB channels.
|
|
*
|
|
* Since the MIOC doesn't have a pci bus attached, we
|
|
* pretend it wasn't there.
|
|
*/
|
|
return (0);
|
|
case 0x84cb8086:
|
|
switch (slot) {
|
|
case 0x12:
|
|
/* Intel 82454NX PXB#0, Bus#A */
|
|
*busnum = read_config(bus, 0x10, func, 0xd0, 1);
|
|
break;
|
|
case 0x13:
|
|
/* Intel 82454NX PXB#0, Bus#B */
|
|
*busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
|
|
break;
|
|
case 0x14:
|
|
/* Intel 82454NX PXB#1, Bus#A */
|
|
*busnum = read_config(bus, 0x10, func, 0xd3, 1);
|
|
break;
|
|
case 0x15:
|
|
/* Intel 82454NX PXB#1, Bus#B */
|
|
*busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
/* ServerWorks -- vendor 0x1166 */
|
|
case 0x00051166:
|
|
case 0x00061166:
|
|
case 0x00081166:
|
|
case 0x00091166:
|
|
case 0x00101166:
|
|
case 0x00111166:
|
|
case 0x00171166:
|
|
case 0x01011166:
|
|
case 0x010f1014:
|
|
case 0x02011166:
|
|
case 0x03021014:
|
|
*busnum = read_config(bus, slot, func, 0x44, 1);
|
|
break;
|
|
|
|
/* Compaq/HP -- vendor 0x0e11 */
|
|
case 0x60100e11:
|
|
*busnum = read_config(bus, slot, func, 0xc8, 1);
|
|
break;
|
|
default:
|
|
/* Don't know how to read bus number. */
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|