6174e6ed12
controllers typically have multiple channels and support a number of serial communications protocols. The scc(4) driver is itself an umbrella driver that delegates the control over each channel and mode to a subordinate driver (like uart(4)). The scc(4) driver supports the Siemens SAB 82532 and the Zilog Z8530 and replaces puc(4) for these devices.
52 lines
1.8 KiB
C
52 lines
1.8 KiB
C
/*-
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* Copyright (c) 2004-2006 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_SCC_BUS_H_
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#define _DEV_SCC_BUS_H_
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#include <sys/serial.h>
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#include <serdev_if.h>
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#define SCC_IVAR_CHANNEL 0
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#define SCC_IVAR_CLASS 1
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#define SCC_IVAR_CLOCK 2
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#define SCC_IVAR_MODE 3
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#define SCC_IVAR_REGSHFT 4
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#define SCC_IVAR_HWMTX 5
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/* Hardware class -- the SCC type. */
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#define SCC_CLASS_SAB82532 0
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#define SCC_CLASS_Z8530 1
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/* The possible modes supported by the SCC. */
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#define SCC_MODE_ASYNC 0x01
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#define SCC_MODE_BISYNC 0x02
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#define SCC_MODE_HDLC 0x04
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#endif /* _DEV_SCC_BUS_H_ */
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