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freebsd-skq/sys/mips/sibyte
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neel 78a2d25433 Add support for CPUs with cache coherent DMA. The two main changes are: 
- We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT
  requests on these CPUs.

- The bus_dmamap_sync() is a no-op for these CPUs.

A side-effect of this change is rename DMAMAP_COHERENT flag to
DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately.

Reviewed by: gonzo, imp
2010-03-04 05:23:08 +00:00
..
ata_zbbus.c
files.sibyte With this commit our friend RMI will now compile. I have 2009-10-30 08:53:11 +00:00
sb_asm.S Various fixes to get the SWARM config working on a big-endian Sibyte CPU. 2010-02-17 06:43:37 +00:00
sb_bus_space.h Various fixes to get the SWARM config working on a big-endian Sibyte CPU. 2010-02-17 06:43:37 +00:00
sb_machdep.c Add support for CPUs with cache coherent DMA. The two main changes are: 2010-03-04 05:23:08 +00:00
sb_scd.c SMP support for the mips port. 2010-02-09 06:24:43 +00:00
sb_scd.h SMP support for the mips port. 2010-02-09 06:24:43 +00:00
sb_zbbus.c SMP support for the mips port. 2010-02-09 06:24:43 +00:00
sb_zbpci.c Various fixes to get the SWARM config working on a big-endian Sibyte CPU. 2010-02-17 06:43:37 +00:00