f55bd0e579
Enabled driver initialization causes an abort on the NXP LS1028ARDB platform (without any external endpoints connected). Temporarily disable qoriq_dw_pci probe, so that to allow successful booting of the OS. Submitted by: Lukasz Hajec <lha@semihalf.com> Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D30229
263 lines
6.5 KiB
C
263 lines
6.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* Layerscape DesignWare PCIe driver */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/devmap.h>
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#include <sys/proc.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofwpci.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <dev/pci/pci_dw.h>
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#include "pcib_if.h"
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#include "pci_dw_if.h"
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#define PCIE_ABSERR 0x8D0
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struct qoriq_dw_pci_cfg {
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uint32_t pex_pf0_dgb; /* offset of PEX_PF0_DBG register */
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uint32_t ltssm_bit; /* LSB bit of of LTSSM state field */
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};
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struct qorif_dw_pci_softc {
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struct pci_dw_softc dw_sc;
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device_t dev;
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phandle_t node;
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struct resource *irq_res;
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void *intr_cookie;
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struct qoriq_dw_pci_cfg *soc_cfg;
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};
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static struct qoriq_dw_pci_cfg ls1043_cfg = {
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.pex_pf0_dgb = 0x10000 + 0x7FC,
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.ltssm_bit = 24,
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};
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static struct qoriq_dw_pci_cfg ls1012_cfg = {
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.pex_pf0_dgb = 0x80000 + 0x407FC,
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.ltssm_bit = 24,
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};
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static struct qoriq_dw_pci_cfg ls2080_cfg = {
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.pex_pf0_dgb = 0x80000 + 0x7FC,
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.ltssm_bit = 0,
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};
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static struct qoriq_dw_pci_cfg ls2028_cfg = {
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.pex_pf0_dgb = 0x80000 + 0x407FC,
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.ltssm_bit = 0,
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};
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/* Compatible devices. */
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static struct ofw_compat_data compat_data[] = {
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{"fsl,ls1012a-pcie", (uintptr_t)&ls1012_cfg},
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/*
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* XXX: On LS1028ARDB attaching this driver causes external abort.
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* Disable it for now.
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*/
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#ifdef notyet
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{"fsl,ls1028a-pcie", (uintptr_t)&ls2028_cfg},
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#endif
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{"fsl,ls1043a-pcie", (uintptr_t)&ls1043_cfg},
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{"fsl,ls1046a-pcie", (uintptr_t)&ls1012_cfg},
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{"fsl,ls2080a-pcie", (uintptr_t)&ls2080_cfg},
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{"fsl,ls2085a-pcie", (uintptr_t)&ls2080_cfg},
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{"fsl,ls2088a-pcie", (uintptr_t)&ls2028_cfg},
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{"fsl,ls1088a-pcie", (uintptr_t)&ls2028_cfg},
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{NULL, 0},
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};
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static void
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qorif_dw_pci_dbi_protect(struct qorif_dw_pci_softc *sc, bool protect)
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{
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uint32_t reg;
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reg = pci_dw_dbi_rd4(sc->dev, DW_MISC_CONTROL_1);
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if (protect)
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reg &= ~DBI_RO_WR_EN;
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else
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reg |= DBI_RO_WR_EN;
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pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg);
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}
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static int qorif_dw_pci_intr(void *arg)
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{
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#if 0
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struct qorif_dw_pci_softc *sc = arg;
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uint32_t cause1, cause2;
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/* Ack all interrups */
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cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1);
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cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2);
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pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1);
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pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2);
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#endif
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return (FILTER_HANDLED);
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}
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static int
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qorif_dw_pci_get_link(device_t dev, bool *status)
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{
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struct qorif_dw_pci_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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reg = pci_dw_dbi_rd4(sc->dev, sc->soc_cfg->pex_pf0_dgb);
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reg >>= sc->soc_cfg->ltssm_bit;
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reg &= 0x3F;
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*status = (reg = 0x11) ? true: false;
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return (0);
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}
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static void
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qorif_dw_pci_init(struct qorif_dw_pci_softc *sc)
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{
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// ls_pcie_disable_outbound_atus(pcie);
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/* Forward error response */
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pci_dw_dbi_wr4(sc->dev, PCIE_ABSERR, 0x9401);
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qorif_dw_pci_dbi_protect(sc, true);
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pci_dw_dbi_wr1(sc->dev, PCIR_HDRTYPE, 1);
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qorif_dw_pci_dbi_protect(sc, false);
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// ls_pcie_drop_msg_tlp(pcie);
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}
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static int
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qorif_dw_pci_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "NPX Layaerscape PCI-E Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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qorif_dw_pci_attach(device_t dev)
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{
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struct qorif_dw_pci_softc *sc;
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phandle_t node;
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int rv;
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int rid;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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sc->dev = dev;
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sc->node = node;
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sc->soc_cfg = (struct qoriq_dw_pci_cfg *)
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ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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rid = 0;
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sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->dw_sc.dbi_res == NULL) {
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device_printf(dev, "Cannot allocate DBI memory\n");
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rv = ENXIO;
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goto out;
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}
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/* PCI interrupt */
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->irq_res == NULL) {
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device_printf(dev, "Cannot allocate IRQ resources\n");
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rv = ENXIO;
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goto out;
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}
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rv = pci_dw_init(dev);
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if (rv != 0)
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goto out;
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qorif_dw_pci_init(sc);
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/* Setup interrupt */
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if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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qorif_dw_pci_intr, NULL, sc, &sc->intr_cookie)) {
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device_printf(dev, "cannot setup interrupt handler\n");
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rv = ENXIO;
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goto out;
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}
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return (bus_generic_attach(dev));
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out:
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/* XXX Cleanup */
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return (rv);
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}
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static device_method_t qorif_dw_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, qorif_dw_pci_probe),
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DEVMETHOD(device_attach, qorif_dw_pci_attach),
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DEVMETHOD(pci_dw_get_link, qorif_dw_pci_get_link),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(pcib, qorif_dw_pci_driver, qorif_dw_pci_methods,
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sizeof(struct qorif_dw_pci_softc), pci_dw_driver);
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static devclass_t qorif_dw_pci_devclass;
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DRIVER_MODULE( qorif_dw_pci, simplebus, qorif_dw_pci_driver, qorif_dw_pci_devclass,
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NULL, NULL);
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