141 lines
7.0 KiB
C
141 lines
7.0 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
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* Copyright (c) 2015-2016 Justin Hibbits <jhibbits@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* ATA register defines */
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#define ATA_FEATURE 1 /* (W) feature */
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#define ATA_F_DMA 0x01 /* enable DMA */
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#define ATA_F_OVL 0x02 /* enable overlap */
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#define ATA_COUNT 2 /* (W) sector count */
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#define ATA_SECTOR 3 /* (RW) sector # */
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#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
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#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
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#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
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#define ATA_D_LBA 0x40 /* use LBA addressing */
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#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
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#define ATA_COMMAND 7 /* (W) command */
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#define ATA_ERROR 8 /* (R) error */
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#define ATA_E_ILI 0x01 /* illegal length */
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#define ATA_E_NM 0x02 /* no media */
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#define ATA_E_ABORT 0x04 /* command aborted */
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#define ATA_E_MCR 0x08 /* media change request */
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#define ATA_E_IDNF 0x10 /* ID not found */
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#define ATA_E_MC 0x20 /* media changed */
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#define ATA_E_UNC 0x40 /* uncorrectable data */
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#define ATA_E_ICRC 0x80 /* UDMA crc error */
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#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
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#define ATA_IREASON 9 /* (R) interrupt reason */
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#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
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#define ATA_I_IN 0x02 /* read (1) | write (0) */
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#define ATA_I_RELEASE 0x04 /* released bus (1) */
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#define ATA_I_TAGMASK 0xf8 /* tag mask */
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#define ATA_STATUS 10 /* (R) status */
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#define ATA_ALTSTAT 11 /* (R) alternate status */
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#define ATA_S_ERROR 0x01 /* error */
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#define ATA_S_INDEX 0x02 /* index */
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#define ATA_S_CORR 0x04 /* data corrected */
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#define ATA_S_DRQ 0x08 /* data request */
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#define ATA_S_DSC 0x10 /* drive seek completed */
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#define ATA_S_SERVICE 0x10 /* drive needs service */
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#define ATA_S_DWF 0x20 /* drive write fault */
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#define ATA_S_DMA 0x20 /* DMA ready */
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#define ATA_S_READY 0x40 /* drive ready */
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#define ATA_S_BUSY 0x80 /* busy */
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#define ATA_CONTROL 12 /* (W) control */
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#define ATA_A_IDS 0x02 /* disable interrupts */
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#define ATA_A_RESET 0x04 /* RESET controller */
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#define ATA_A_4BIT 0x08 /* 4 head bits */
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#define ATA_A_HOB 0x80 /* High Order Byte enable */
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/* SATA register defines */
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#define ATA_SSTATUS 13
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#define ATA_SS_DET_MASK 0x0000000f
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#define ATA_SS_DET_NO_DEVICE 0x00000000
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#define ATA_SS_DET_DEV_PRESENT 0x00000001
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#define ATA_SS_DET_PHY_ONLINE 0x00000003
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#define ATA_SS_DET_PHY_OFFLINE 0x00000004
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#define ATA_SS_SPD_MASK 0x000000f0
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#define ATA_SS_SPD_NO_SPEED 0x00000000
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#define ATA_SS_SPD_GEN1 0x00000010
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#define ATA_SS_SPD_GEN2 0x00000020
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#define ATA_SS_SPD_GEN3 0x00000030
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#define ATA_SS_IPM_MASK 0x00000f00
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#define ATA_SS_IPM_NO_DEVICE 0x00000000
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#define ATA_SS_IPM_ACTIVE 0x00000100
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#define ATA_SS_IPM_PARTIAL 0x00000200
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#define ATA_SS_IPM_SLUMBER 0x00000600
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#define ATA_SS_IPM_DEVSLEEP 0x00000800
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#define ATA_SERROR 14
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#define ATA_SE_DATA_CORRECTED 0x00000001
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#define ATA_SE_COMM_CORRECTED 0x00000002
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#define ATA_SE_DATA_ERR 0x00000100
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#define ATA_SE_COMM_ERR 0x00000200
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#define ATA_SE_PROT_ERR 0x00000400
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#define ATA_SE_HOST_ERR 0x00000800
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#define ATA_SE_PHY_CHANGED 0x00010000
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#define ATA_SE_PHY_IERROR 0x00020000
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#define ATA_SE_COMM_WAKE 0x00040000
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#define ATA_SE_DECODE_ERR 0x00080000
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#define ATA_SE_PARITY_ERR 0x00100000
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#define ATA_SE_CRC_ERR 0x00200000
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#define ATA_SE_HANDSHAKE_ERR 0x00400000
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#define ATA_SE_LINKSEQ_ERR 0x00800000
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#define ATA_SE_TRANSPORT_ERR 0x01000000
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#define ATA_SE_UNKNOWN_FIS 0x02000000
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#define ATA_SE_EXCHANGED 0x04000000
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#define ATA_SCONTROL 15
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#define ATA_SC_DET_MASK 0x0000000f
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#define ATA_SC_DET_IDLE 0x00000000
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#define ATA_SC_DET_RESET 0x00000001
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#define ATA_SC_DET_DISABLE 0x00000004
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#define ATA_SC_SPD_MASK 0x000000f0
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#define ATA_SC_SPD_NO_SPEED 0x00000000
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#define ATA_SC_SPD_SPEED_GEN1 0x00000010
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#define ATA_SC_SPD_SPEED_GEN2 0x00000020
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#define ATA_SC_SPD_SPEED_GEN3 0x00000030
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#define ATA_SC_IPM_MASK 0x00000f00
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#define ATA_SC_IPM_NONE 0x00000000
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#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
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#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
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#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
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