fb5fbfc750
things over floppy size limits, I can exclude it for release builds or something like that. Most of the changes are to get the load_elf.c file into a seperate elf32_ or elf64_ namespace so that you can have two ELF loaders present at once. Note that for 64 bit kernels, it actually starts up the kernel already in 64 bit mode with paging enabled. This is really easy because we have a known minimum feature set. Of note is that for amd64, we have to pass in the bios int 15 0xe821 memory map because once in long mode, you absolutely cannot make VM86 calls. amd64 does not use 'struct bootinfo' at all. It is a pure loader metadata startup, just like sparc64 and powerpc. Much of the infrastructure to support this was adapted from sparc64.
114 lines
2.8 KiB
ArmAsm
114 lines
2.8 KiB
ArmAsm
/*-
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* Copyright (c) 2003 Peter Wemm <peter@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Quick and dirty trampoline to get into 64 bit (long) mode and running
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* with paging enabled so that we enter the kernel at its linked address.
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*/
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#define MSR_EFER 0xc0000080
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#define EFER_LME 0x00000100
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#define CR4_PAE 0x00000020
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#define CR4_PSE 0x00000010
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#define CR0_PG 0x80000000
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/* GRRR. Deal with BTX that links us for a non-zero location */
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#define VPBASE 0xa000
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#define VTOP(x) ((x) + VPBASE)
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.data
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.p2align 12,0x40
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.globl PT4
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PT4:
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.space 0x1000
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.globl PT3
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PT3:
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.space 0x1000
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.globl PT2
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PT2:
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.space 0x1000
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gdtdesc:
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.word gdtend - gdt
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.long VTOP(gdt) # low
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.long 0 # high
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gdt:
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.long 0 # null descriptor
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.long 0
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.long 0x00000000 # %cs
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.long 0x00209800
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.long 0x00000000 # %ds
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.long 0x00008000
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gdtend:
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.text
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.code32
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.globl amd64_tramp
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amd64_tramp:
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/* Be sure that interrupts are disabled */
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cli
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/* Turn on EFER.LME */
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movl $MSR_EFER, %ecx
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rdmsr
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orl $EFER_LME, %eax
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wrmsr
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/* Turn on PAE */
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movl %cr4, %eax
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orl $(CR4_PAE | CR4_PSE), %eax
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movl %eax, %cr4
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/* Set %cr3 for PT4 */
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movl $VTOP(PT4), %eax
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movl %eax, %cr3
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/* Turn on paging (implicitly sets EFER.LMA) */
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movl %cr0, %eax
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orl $CR0_PG, %eax
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movl %eax, %cr0
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/* Now we're in compatability mode. set %cs for long mode */
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movl $VTOP(gdtdesc), %eax
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movl VTOP(entry_hi), %esi
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movl VTOP(entry_lo), %edi
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lgdt (%eax)
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ljmp $0x8, $VTOP(longmode)
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.code64
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longmode:
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/* We're still running V=P, jump to entry point */
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movl %esi, %eax
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salq $32, %rax
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movl %edi, %eax
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pushq %rax
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ret
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