c3e289e1ce
Kernel sources for 64-bit PowerPC, along with build-system changes to keep 32-bit kernels compiling (build system changes for 64-bit kernels are coming later). Existing 32-bit PowerPC kernel configurations must be updated after this change to specify their architecture.
344 lines
7.4 KiB
C
344 lines
7.4 KiB
C
/*-
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* Copyright (c) 2009 Nathan Whitehorn
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <dev/ofw/ofw_bus.h>
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#include "cpufreq_if.h"
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struct pcr_softc {
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device_t dev;
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uint32_t pcr_vals[3];
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int nmodes;
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};
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static void pcr_identify(driver_t *driver, device_t parent);
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static int pcr_probe(device_t dev);
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static int pcr_attach(device_t dev);
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static int pcr_settings(device_t dev, struct cf_setting *sets, int *count);
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static int pcr_set(device_t dev, const struct cf_setting *set);
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static int pcr_get(device_t dev, struct cf_setting *set);
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static int pcr_type(device_t dev, int *type);
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static device_method_t pcr_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, pcr_identify),
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DEVMETHOD(device_probe, pcr_probe),
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DEVMETHOD(device_attach, pcr_attach),
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/* cpufreq interface */
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DEVMETHOD(cpufreq_drv_set, pcr_set),
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DEVMETHOD(cpufreq_drv_get, pcr_get),
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DEVMETHOD(cpufreq_drv_type, pcr_type),
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DEVMETHOD(cpufreq_drv_settings, pcr_settings),
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{0, 0}
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};
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static driver_t pcr_driver = {
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"pcr",
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pcr_methods,
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sizeof(struct pcr_softc)
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};
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static devclass_t pcr_devclass;
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DRIVER_MODULE(pcr, cpu, pcr_driver, pcr_devclass, 0, 0);
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/*
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* States
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*/
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#define PCR_TO_FREQ(a) ((a >> 17) & 3)
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#define PCR_FULL 0
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#define PCR_HALF 1
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#define PCR_QUARTER 2 /* Only on 970MP */
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#define PSR_RECEIVED (1ULL << 61)
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#define PSR_COMPLETED (1ULL << 61)
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/*
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* SCOM addresses
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*/
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#define SCOM_PCR 0x0aa00100 /* Power Control Register */
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#define SCOM_PCR_BIT 0x80000000 /* Data bit for PCR */
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#define SCOM_PSR 0x40800100 /* Power Status Register */
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/*
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* SCOM Glue
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*/
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#define SCOMC_READ 0x00008000
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#define SCOMC_WRITE 0x00000000
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static void
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write_scom(register_t address, uint64_t value)
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{
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register_t msr;
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#ifndef __powerpc64__
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register_t hi, lo, scratch;
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#endif
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msr = mfmsr();
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mtmsr(msr & ~PSL_EE); isync();
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#ifdef __powerpc64__
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mtspr(SPR_SCOMD, value);
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#else
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hi = (value >> 32) & 0xffffffff;
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lo = value & 0xffffffff;
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mtspr64(SPR_SCOMD, hi, lo, scratch);
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#endif
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isync();
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mtspr(SPR_SCOMC, address | SCOMC_WRITE);
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isync();
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mtmsr(msr); isync();
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}
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static uint64_t
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read_scom(register_t address)
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{
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register_t msr;
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uint64_t ret;
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msr = mfmsr();
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mtmsr(msr & ~PSL_EE); isync();
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mtspr(SPR_SCOMC, address | SCOMC_READ);
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isync();
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__asm __volatile ("mfspr %0,%1;"
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" mr %0+1, %0; srdi %0,%0,32" : "=r" (ret) : "K" (SPR_SCOMD));
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(void)mfspr(SPR_SCOMC); /* Complete transcation */
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mtmsr(msr); isync();
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return (ret);
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}
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static void
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pcr_identify(driver_t *driver, device_t parent)
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{
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uint16_t vers;
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vers = mfpvr() >> 16;
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/* Check for an IBM 970-class CPU */
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switch (vers) {
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case IBM970FX:
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case IBM970GX:
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case IBM970MP:
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break;
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default:
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return;
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}
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/* Make sure we're not being doubly invoked. */
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if (device_find_child(parent, "pcr", -1) != NULL)
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return;
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/*
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* We attach a child for every CPU since settings need to
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* be performed on every CPU in the SMP case.
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*/
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if (BUS_ADD_CHILD(parent, 10, "pcr", -1) == NULL)
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device_printf(parent, "add pcr child failed\n");
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}
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static int
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pcr_probe(device_t dev)
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{
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if (resource_disabled("pcr", 0))
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return (ENXIO);
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device_set_desc(dev, "PPC 970 Power Control Register");
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return (0);
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}
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static int
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pcr_attach(device_t dev)
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{
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struct pcr_softc *sc;
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phandle_t cpu;
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uint32_t modes[3];
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int i;
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sc = device_get_softc(dev);
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sc->dev = dev;
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cpu = ofw_bus_get_node(device_get_parent(dev));
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if (cpu <= 0) {
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device_printf(dev,"No CPU device tree node!\n");
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return (ENXIO);
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}
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if (OF_getproplen(cpu, "power-mode-data") <= 0) {
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/* Use the first CPU's node */
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cpu = OF_child(OF_parent(cpu));
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}
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/*
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* Collect the PCR values for each mode from the device tree.
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* These include bus timing information, and so cannot be
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* directly computed.
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*/
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sc->nmodes = OF_getproplen(cpu, "power-mode-data");
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if (sc->nmodes <= 0 || sc->nmodes > sizeof(sc->pcr_vals)) {
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device_printf(dev,"No power mode data in device tree!\n");
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return (ENXIO);
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}
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OF_getprop(cpu, "power-mode-data", modes, sc->nmodes);
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sc->nmodes /= sizeof(modes[0]);
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/* Sort the modes */
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for (i = 0; i < sc->nmodes; i++)
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sc->pcr_vals[PCR_TO_FREQ(modes[i])] = modes[i];
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cpufreq_register(dev);
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return (0);
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}
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static int
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pcr_settings(device_t dev, struct cf_setting *sets, int *count)
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{
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struct pcr_softc *sc;
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sc = device_get_softc(dev);
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if (sets == NULL || count == NULL)
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return (EINVAL);
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if (*count < sc->nmodes)
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return (E2BIG);
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/* Return a list of valid settings for this driver. */
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memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->nmodes);
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sets[0].freq = 10000; sets[0].dev = dev;
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sets[1].freq = 5000; sets[1].dev = dev;
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if (sc->nmodes > 2)
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sets[2].freq = 2500; sets[2].dev = dev;
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*count = sc->nmodes;
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return (0);
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}
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static int
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pcr_set(device_t dev, const struct cf_setting *set)
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{
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struct pcr_softc *sc;
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register_t pcr, msr;
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uint64_t psr;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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/* Construct the new PCR */
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pcr = SCOM_PCR_BIT;
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if (set->freq == 10000)
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pcr |= sc->pcr_vals[0];
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else if (set->freq == 5000)
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pcr |= sc->pcr_vals[1];
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else if (set->freq == 2500)
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pcr |= sc->pcr_vals[2];
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msr = mfmsr();
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mtmsr(msr & ~PSL_EE); isync();
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/* 970MP requires PCR and PCRH to be cleared first */
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write_scom(SCOM_PCR,0); /* Clear PCRH */
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write_scom(SCOM_PCR,SCOM_PCR_BIT); /* Clear PCR */
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/* Set PCR */
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write_scom(SCOM_PCR, pcr);
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/* Wait for completion */
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do {
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DELAY(100);
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psr = read_scom(SCOM_PSR);
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} while ((psr & PSR_RECEIVED) && !(psr & PSR_COMPLETED));
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mtmsr(msr); isync();
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return (0);
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}
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static int
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pcr_get(device_t dev, struct cf_setting *set)
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{
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struct pcr_softc *sc;
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uint64_t psr;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
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psr = read_scom(SCOM_PSR);
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/* We want bits 6 and 7 */
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psr = (psr >> 56) & 3;
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set->freq = 10000;
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if (psr == PCR_HALF)
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set->freq = 5000;
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else if (psr == PCR_QUARTER)
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set->freq = 2500;
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set->dev = dev;
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return (0);
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}
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static int
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pcr_type(device_t dev, int *type)
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{
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if (type == NULL)
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return (EINVAL);
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*type = CPUFREQ_TYPE_RELATIVE;
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return (0);
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}
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