ed8d62c038
RockChip clocks register have a write mask in the upper 16 bits, if a 1 is present the corresponding bit in the lower 16 ones is set. Use this instead of always setting the mask to 0xFFFF0000. This avoids a read of the register. While here, when switching PLL frequency, first switch it to slow mode. When set to slow mode the PLL clock will be the external oscillator. Changing the PLL parameters while its output is used can cause hang (sometimes). MFC after: 1 week
68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright 2018 Emmanuel Vadot <manu@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _RK_CLK_PLL_H_
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#define _RK_CLK_PLL_H_
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#include <dev/extres/clk/clk.h>
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struct rk_clk_pll_rate {
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uint32_t freq;
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uint32_t refdiv;
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uint32_t fbdiv;
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uint32_t postdiv1;
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uint32_t postdiv2;
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uint32_t dsmpd;
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uint32_t frac;
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};
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struct rk_clk_pll_def {
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struct clknode_init_def clkdef;
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uint32_t base_offset;
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uint32_t gate_offset;
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uint32_t gate_shift;
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uint32_t mode_reg;
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uint32_t mode_val;
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uint32_t flags;
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struct rk_clk_pll_rate *rates;
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struct rk_clk_pll_rate *frac_rates;
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};
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#define RK_CLK_PLL_HAVE_GATE 0x1
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int rk3328_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef);
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int rk3399_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef);
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#endif /* _RK_CLK_PLL_H_ */
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