169 lines
5.1 KiB
C
169 lines
5.1 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#ifdef AH_SUPPORT_AR5312
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ar5312/ar5312.h"
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#include "ar5312/ar5312reg.h"
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#include "ar5312/ar5312phy.h"
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#define AR_NUM_GPIO 6 /* 6 GPIO pins */
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#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
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/*
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* Change the LED blinking pattern to correspond to the connectivity
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*/
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void
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ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
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{
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uint32_t val;
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uint32_t resOffset = (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh));
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if(IS_2316(ah)) return; /* not yet */
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val = SM(AR5312_PCICFG_LEDSEL0, AR5312_PCICFG_LEDSEL) |
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SM(AR5312_PCICFG_LEDMOD0, AR5312_PCICFG_LEDMODE) |
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2;
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OS_REG_WRITE(ah, resOffset+AR5312_PCICFG,
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(OS_REG_READ(ah, AR5312_PCICFG) &~
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(AR5312_PCICFG_LEDSEL | AR5312_PCICFG_LEDMODE |
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AR5312_PCICFG_LEDSBR))
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| val);
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}
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/*
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* Detect if our wireless mac is present.
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*/
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HAL_BOOL
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ar5312DetectCardPresent(struct ath_hal *ah)
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{
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uint16_t macVersion, macRev;
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uint32_t v;
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/*
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* Read the Silicon Revision register and compare that
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* to what we read at attach time. If the same, we say
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* a card/device is present.
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*/
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#if (AH_SUPPORT_2316 || AH_SUPPORT_2317)
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if(IS_5315(ah))
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{
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v = (OS_REG_READ(ah,
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(AR5315_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5315_WREV))
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& AR_SREV_ID;
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macVersion = v >> AR_SREV_ID_S;
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macRev = v & AR_SREV_REVISION;
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return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
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AH_PRIVATE(ah)->ah_macRev == macRev);
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}
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else
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#endif
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{
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v = (OS_REG_READ(ah,
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(AR5312_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5312_WREV))
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& AR_SREV_ID;
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macVersion = v >> AR_SREV_ID_S;
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macRev = v & AR_SREV_REVISION;
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return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
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AH_PRIVATE(ah)->ah_macRev == macRev);
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}
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}
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/*
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* If 32KHz clock exists, use it to lower power consumption during sleep
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*
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* Note: If clock is set to 32 KHz, delays on accessing certain
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* baseband registers (27-31, 124-127) are required.
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*/
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void
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ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
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{
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if (ar5212Use32KHzclock(ah, opmode)) {
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/*
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* Enable clocks to be turned OFF in BB during sleep
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* and also enable turning OFF 32MHz/40MHz Refclk
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* from A2.
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*/
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OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
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OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0d);
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OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
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OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
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OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x05);
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OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
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IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
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OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
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OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
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} else {
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OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
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OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
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IS_RAD5112_ANY(ah) ? 39 : 31);
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OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
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OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
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if (IS_5312_2_X(ah)) {
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/* Set ADC/DAC select values */
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OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
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} else {
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OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
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OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
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OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
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OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
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IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
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}
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}
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}
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/*
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* If 32KHz clock exists, turn it off and turn back on the 32Mhz
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*/
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void
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ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
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{
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if (ar5212Use32KHzclock(ah, opmode)) {
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/* # Set sleep clock rate back to 32 MHz. */
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OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
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OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
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IS_RAD5112_ANY(ah) ? 39 : 31);
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/*
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* Restore BB registers to power-on defaults
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*/
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OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
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OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
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if (IS_5312_2_X(ah)) {
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/* Set ADC/DAC select values */
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OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
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} else {
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OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
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OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
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OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
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OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
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IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
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}
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}
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}
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#endif /* AH_SUPPORT_AR5312 */
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