b8cb0864dc
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs. As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts. This is a preparation patch for NXP LS1046A SoC support. Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351
97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2020 Alstom Group.
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* Copyright (c) 2020 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _QORIQ_CLKGEN_H_
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#define _QORIQ_CLKGEN_H_
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <arm64/qoriq/clk/qoriq_clk_pll.h>
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#define QORIQ_CLK_NAME_MAX_LEN 32
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#define QORIQ_LITTLE_ENDIAN 0x01
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#define QORIQ_TYPE_SYSCLK 0
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#define QORIQ_TYPE_CMUX 1
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#define QORIQ_TYPE_HWACCEL 2
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#define QORIQ_TYPE_FMAN 3
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#define QORIQ_TYPE_PLATFORM_PLL 4
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#define QORIQ_TYPE_CORECLK 5
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#define QORIQ_TYPE_INTERNAL 6
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#define PLL_DIV1 0
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#define PLL_DIV2 1
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#define PLL_DIV3 2
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#define PLL_DIV4 3
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#define PLL_DIV5 4
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#define PLL_DIV6 5
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#define PLL_DIV7 6
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#define PLL_DIV8 7
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#define PLL_DIV9 8
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#define PLL_DIV10 9
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#define PLL_DIV11 10
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#define PLL_DIV12 11
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#define PLL_DIV13 12
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#define PLL_DIV14 13
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#define PLL_DIV15 14
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#define PLL_DIV16 15
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#define QORIQ_CLK_ID(_type, _index) ((_type << 8) + _index)
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#define QORIQ_SYSCLK_NAME "clockgen_sysclk"
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#define QORIQ_CORECLK_NAME "clockgen_coreclk"
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typedef int (*qoriq_init_func_t)(device_t);
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struct qoriq_clkgen_softc {
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device_t dev;
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struct resource *res;
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struct clkdom *clkdom;
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struct mtx mtx;
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struct qoriq_clk_pll_def *pltfrm_pll_def;
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struct qoriq_clk_pll_def **cga_pll;
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int cga_pll_num;
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struct clk_mux_def **mux;
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int mux_num;
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qoriq_init_func_t init_func;
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uint32_t flags;
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bool has_coreclk;
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};
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MALLOC_DECLARE(M_QORIQ_CLKGEN);
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DECLARE_CLASS(qoriq_clkgen_driver);
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int qoriq_clkgen_attach(device_t);
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#endif /* _QORIQ_CLKGEN_H_ */
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