411 lines
14 KiB
Groff
411 lines
14 KiB
Groff
.\" Copyright (c) 2010 George Neville-Neil. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" This software is provided by ``as is'' and
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.\" any express or implied warranties, including, but not limited to, the
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.\" implied warranties of merchantability and fitness for a particular purpose
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.\" are disclaimed. in no event shall George Neville-Neil be liable
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.\" for any direct, indirect, incidental, special, exemplary, or consequential
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.\" damages (including, but not limited to, procurement of substitute goods
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.\" or services; loss of use, data, or profits; or business interruption)
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.\" however caused and on any theory of liability, whether in contract, strict
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.\" liability, or tort (including negligence or otherwise) arising in any way
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.\" out of the use of this software, even if advised of the possibility of
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.\" such damage.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 11, 2010
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.Os
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.Dt PMC.MIPS 3
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.Sh NAME
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.Nm pmc.mips
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.Nd measurement events for
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.Tn MIPS
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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MIPS PMCs are present in MIPS
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.Tn "24k"
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and other processors in the MIPS family.
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.Pp
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There are two counters supported by the hardware and each is 32 bits
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wide.
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.Pp
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MIPS PMCs are documented in
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.Rs
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.%B "MIPS32 24K Processor Core Family Software User's Manual"
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.%D December 2008
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.%Q "MIPS Technologies Inc."
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.Re
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.Ss Event Specifiers (Programmable PMCs)
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MIPS programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li CYCLE
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.Pq Event 0, Counter 0/1
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Total number of cycles.
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The performance counters are clocked by the
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top-level gated clock.
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If the core is built with that clock gater
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present, none of the counters will increment while the clock is
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stopped - due to a WAIT instruction.
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.It Li INSTR_EXECUTED
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.Pq Event 1, Counter 0/1
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Total number of instructions completed.
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.It Li BRANCH_COMPLETED
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.Pq Event 2, Counter 0
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Total number of branch instructions completed.
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.It Li BRANCH_MISPRED
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.Pq Event 2, Counter 1
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Counts all branch instructions which completed, but were mispredicted.
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.It Li RETURN
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.Pq Event 3, Counter 0
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Counts all JR R31 instructions completed.
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.It Li RETURN_MISPRED
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.Pq Event 3, Counter 1
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Counts all JR $31 instructions which completed, used the RPS for a prediction, but were mispredicted.
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.It Li RETURN_NOT_31
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.Pq Event 4, Counter 0
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Counts all JR $xx (not $31) and JALR instructions (indirect jumps).
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.It Li RETURN_NOTPRED
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.Pq Event 4, Counter 1
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If RPS use is disabled, JR $31 will not be predicted.
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.It Li ITLB_ACCESS
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.Pq Event 5, Counter 0
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Counts ITLB accesses that are due to fetches showing up in the
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instruction fetch stage of the pipeline and which do not use a fixed
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mapping or are not in unmapped space.
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If an address is fetched twice from the pipe (as in the case of a
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cache miss), that instruction willcount as 2 ITLB accesses.
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Since each fetch gets us 2 instructions,there is one access marked per double
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word.
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.It Li ITLB_MISS
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.Pq Event 5, Counter 1
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Counts all misses in the ITLB except ones that are on the back of another
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miss.
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We cannot process back to back misses and thus those are
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ignored.
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They are also ignored if there is some form of address error.
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.It Li DTLB_ACCESS
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.Pq Event 6, Counter 0
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Counts DTLB access including those in unmapped address spaces.
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.It Li DTLB_MISS
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.Pq Event 6, Counter 1
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Counts DTLB misses. Back to back misses that result in only one DTLB
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entry getting refilled are counted as a single miss.
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.It Li JTLB_IACCESS
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.Pq Event 7, Counter 0
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Instruction JTLB accesses are counted exactly the same as ITLB misses.
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.It Li JTLB_IMISS
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.Pq Event 7, Counter 1
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Counts instruction JTLB accesses that result in no match or a match on
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an invalid translation.
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.It Li JTLB_DACCESS
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.Pq Event 8, Counter 0
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Data JTLB accesses.
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.It Li JTLB_DMISS
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.Pq Event 8, Counter 1
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Counts data JTLB accesses that result in no match or a match on an invalid translation.
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.It Li IC_FETCH
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.Pq Event 9, Counter 0
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Counts every time the instruction cache is accessed. All replays,
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wasted fetches etc. are counted.
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For example, following a branch, even though the prediction is taken,
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the fall through access is counted.
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.It Li IC_MISS
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.Pq Event 9, Counter 1
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Counts all instruction cache misses that result in a bus request.
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.It Li DC_LOADSTORE
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.Pq Event 10, Counter 0
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Counts cached loads and stores.
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.It Li DC_WRITEBACK
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.Pq Event 10, Counter 1
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Counts cache lines written back to memory due to replacement or cacheops.
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.It Li DC_MISS
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.Pq Event 11, Counter 0/1
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Counts loads and stores that miss in the cache
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.It Li LOAD_MISS
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.Pq Event 13, Counter 0
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Counts number of cacheable loads that miss in the cache.
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.It Li STORE_MISS
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.Pq Event 13, Counter 1
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Counts number of cacheable stores that miss in the cache.
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.It Li INTEGER_COMPLETED
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.Pq Event 14, Counter 0
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Non-floating point, non-Coprocessor 2 instructions.
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.It Li FP_COMPLETED
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.Pq Event 14, Counter 1
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Floating point instructions completed.
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.It Li LOAD_COMPLETED
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.Pq Event 15, Counter 0
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Integer and co-processor loads completed.
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.It Li STORE_COMPLETED
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.Pq Event 15, Counter 1
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Integer and co-processor stores completed.
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.It Li BARRIER_COMPLETED
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.Pq Event 16, Counter 0
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Direct jump (and link) instructions completed.
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.It Li MIPS16_COMPLETED
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.Pq Event 16, Counter 1
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MIPS16c instructions completed.
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.It Li NOP_COMPLETED
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.Pq Event 17, Counter 0
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NOPs completed.
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This includes all instructions that normally write to a general
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purpose register, but where the destination register was set to r0.
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.It Li INTEGER_MULDIV_COMPLETED
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.Pq Event 17, Counter 1
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Integer multipy and divide instructions completed. (MULxx, DIVx, MADDx, MSUBx).
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.It Li RF_STALL
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.Pq Event 18, Counter 0
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Counts the total number of cycles where no instructions are issued
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from the IFU to ALU (the RF stage does not advance) which includes
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both of the previous two events.
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The RT_STALL is different than the sum of them though because cycles
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when both stalls are active will only be counted once.
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.It Li INSTR_REFETCH
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.Pq Event 18, Counter 1
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replay traps (other than uTLB)
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.It Li STORE_COND_COMPLETED
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.Pq Event 19, Counter 0
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Conditional stores completed. Counts all events, including failed stores.
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.It Li STORE_COND_FAILED
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.Pq Event 19, Counter 1
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Conditional store instruction that did not update memory.
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Note: While this event and the SC instruction count event can be configured to
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count in specific operating modes, the timing of the events is much
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different and the observed operating mode could change between them,
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causing some inaccuracy in the measured ratio.
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.It Li ICACHE_REQUESTS
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.Pq Event 20, Counter 0
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Note that this only counts PREFs that are actually attempted.
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PREFs to uncached addresses or ones with translation errors are not counted
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.It Li ICACHE_HIT
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.Pq Event 20, Counter 1
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Counts PREF instructions that hit in the cache
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.It Li L2_WRITEBACK
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.Pq Event 21, Counter 0
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Counts cache lines written back to memory due to replacement or cacheops.
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.It Li L2_ACCESS
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.Pq Event 21, Counter 1
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Number of accesses to L2 Cache.
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.It Li L2_MISS
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.Pq Event 22, Counter 0
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Number of accesses that missed in the L2 cache.
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.It Li L2_ERR_CORRECTED
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.Pq Event 22, Counter 1
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Single bit errors in L2 Cache that were detected and corrected.
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.It Li EXCEPTIONS
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.Pq Event 23, Counter 0
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Any type of exception taken.
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.It Li RF_CYCLES_STALLED
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.Pq Event 24, Counter 0
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Counts cycles where the LSU is in fixup and cannot accept a new
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instruction from the ALU.
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Fixups are replays within the LSU that occur when an instruction needs
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to re-access the cache or the DTLB.
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.It Li IFU_CYCLES_STALLED
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.Pq Event 25, Counter 0
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Counts the number of cycles where the fetch unit is not providing a
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valid instruction to the ALU.
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.It Li ALU_CYCLES_STALLED
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.Pq Event 25, Counter 1
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Counts the number of cycles where the ALU pipeline cannot advance.
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.It Li UNCACHED_LOAD
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.Pq Event 33, Counter 0
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Counts uncached and uncached accelerated loads.
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.It Li UNCACHED_STORE
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.Pq Event 33, Counter 1
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Counts uncached and uncached accelerated stores.
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.It Li CP2_REG_TO_REG_COMPLETED
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.Pq Event 35, Counter 0
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Co-processor 2 register to register instructions completed.
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.It Li MFTC_COMPLETED
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.Pq Event 35, Counter 1
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Co-processor 2 move to and from instructions as well as loads and stores.
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.It Li IC_BLOCKED_CYCLES
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.Pq Event 37, Counter 0
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Cycles when IFU stalls because an instruction miss caused the IFU not
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to have any runnable instructions.
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Ignores the stalls due to ITLB misses as well as the 4 cycles
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following a redirect.
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.It Li DC_BLOCKED_CYCLES
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.Pq Event 37, Counter 1
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Counts all cycles where integer pipeline waits on Load return data due
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to a D-cache miss.
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The LSU can signal a "long stall" on a D-cache misses, in which case
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the waiting TC might be rescheduled so other TCs can execute
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instructions till the data returns.
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.It Li L2_IMISS_STALL_CYCLES
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.Pq Event 38, Counter 0
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Cycles where the main pipeline is stalled waiting for a SYNC to complete.
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.It Li L2_DMISS_STALL_CYCLES
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.Pq Event 38, Counter 1
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Cycles where the main pipeline is stalled because of an index conflict
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in the Fill Store Buffer.
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.It Li DMISS_CYCLES
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.Pq Event 39, Counter 0
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Data miss is outstanding, but not necessarily stalling the pipeline.
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The difference between this and D$ miss stall cycles can show the gain
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from non-blocking cache misses.
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.It Li L2_MISS_CYCLES
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.Pq Event 39, Counter 1
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L2 miss is outstanding, but not necessarily stalling the pipeline.
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.It Li UNCACHED_BLOCK_CYCLES
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.Pq Event 40, Counter 0
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Cycles where the processor is stalled on an uncached fetch, load, or store.
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.It Li MDU_STALL_CYCLES
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.Pq Event 41, Counter 0
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Cycles where the processor is stalled on an uncached fetch, load, or store.
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.It Li FPU_STALL_CYCLES
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.Pq Event 41, Counter 1
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Counts all cycles where integer pipeline waits on FPU return data.
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.It Li CP2_STALL_CYCLES
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.Pq Event 42, Counter 0
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Counts all cycles where integer pipeline waits on CP2 return data.
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.It Li COREXTEND_STALL_CYCLES
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.Pq Event 42, Counter 1
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Counts all cycles where integer pipeline waits on CorExtend return data.
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.It Li ISPRAM_STALL_CYCLES
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.Pq Event 43, Counter 0
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Count all pipeline bubbles that are a result of multicycle ISPRAM
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access.
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Pipeline bubbles are defined as all cycles that IFU doesn't present an
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instruction to ALU. The four cycles after a redirect are not counted.
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.It Li DSPRAM_STALL_CYCLES
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.Pq Event 43, Counter 1
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Counts stall cycles created by an instruction waiting for access to DSPRAM.
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.It Li CACHE_STALL_CYCLES
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.Pq Event 44, Counter 0
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Counts all cycles the where pipeline is stalled due to CACHE
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instructions.
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Includes cycles where CACHE instructions themselves are
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stalled in the ALU, and cycles where CACHE instructions cause
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subsequent instructions to be stalled.
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.It Li LOAD_TO_USE_STALLS
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.Pq Event 45, Counter 0
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Counts all cycles where integer pipeline waits on Load return data.
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.It Li BASE_MISPRED_STALLS
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.Pq Event 45, Counter 1
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Counts stall cycles due to skewed ALU where the bypass to the address
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generation takes an extra cycle.
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.It Li CPO_READ_STALLS
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.Pq Event 46, Counter 0
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Counts all cycles where integer pipeline waits on return data from
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MFC0, RDHWR instructions.
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.It Li BRANCH_MISPRED_CYCLES
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.Pq Event 46, Counter 1
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This counts the number of cycles from a mispredicted branch until the
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next non-delay slot instruction executes.
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.It Li IFETCH_BUFFER_FULL
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.Pq Event 48, Counter 0
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Counts the number of times an instruction cache miss was detected, but
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both fill buffers were already allocated.
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.It Li FETCH_BUFFER_ALLOCATED
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.Pq Event 48, Counter 1
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Number of cycles where at least one of the IFU fill buffers is
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allocated (miss pending).
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.It Li EJTAG_ITRIGGER
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.Pq Event 49, Counter 0
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Number of times an EJTAG Instruction Trigger Point condition matched.
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.It Li EJTAG_DTRIGGER
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.Pq Event 49, Counter 1
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Number of times an EJTAG Data Trigger Point condition matched.
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.It Li FSB_LT_QUARTER
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.Pq Event 50, Counter 0
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Fill store buffer less than one quarter full.
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.It Li FSB_QUARTER_TO_HALF
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.Pq Event 50, Counter 1
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Fill store buffer between one quarter and one half full.
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.It Li FSB_GT_HALF
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.Pq Event 51, Counter 0
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Fill store buffer more than half full.
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.It Li FSB_FULL_PIPELINE_STALLS
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.Pq Event 51, Counter 1
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Cycles where the pipeline is stalled because the Fill-Store Buffer in LSU is full.
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.It Li LDQ_LT_QUARTER
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.Pq Event 52, Counter 0
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Load data queue less than one quarter full.
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.It Li LDQ_QUARTER_TO_HALF
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.Pq Event 52, Counter 1
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Load data queue between one quarter and one half full.
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.It Li LDQ_GT_HALF
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.Pq Event 53, Counter 0
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Load data queue more than one half full.
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.It Li LDQ_FULL_PIPELINE_STALLS
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.Pq Event 53, Counter 1
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Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full.
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.It Li WBB_LT_QUARTER
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.Pq Event 54, Counter 0
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Write back buffer less than one quarter full.
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.It Li WBB_QUARTER_TO_HALF
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.Pq Event 54, Counter 1
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Write back buffer between one quarter and one half full.
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.It Li WBB_GT_HALF
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.Pq Event 55, Counter 0
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Write back buffer more than one half full.
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.It Li WBB_FULL_PIPELINE_STALLS
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.Pq Event 55 Counter 1
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Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full.
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.It Li REQUEST_LATENCY
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.Pq Event 61, Counter 0
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Measures latency from miss detection until critical dword of response
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is returned, Only counts for cacheable reads.
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.It Li REQUEST_COUNT
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.Pq Event 61, Counter 1
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Counts number of cacheable read requests used for previous latency counter.
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.El
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.Ss Event Name Aliases
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The following table shows the mapping between the PMC-independent
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aliases supported by
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.Lb libpmc
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and the underlying hardware events used.
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.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
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.It Em Alias Ta Em Event Ta
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.It Li instructions Ta Li INSTR_EXECUTED Ta
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.It Li branches Ta Li BRANCH_COMPLETED Ta
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.It Li branch-mispredicts Ta Li BRANCH_MISPRED Ta
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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.Xr pmc.atom 3 ,
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.Xr pmc.core 3 ,
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc_cpuinfo 3 ,
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.Xr pmclog 3 ,
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.Xr hwpmc 4
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.Sh HISTORY
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The
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.Nm pmc
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library first appeared in
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.Fx 6.0 .
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.Sh AUTHORS
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The
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.Lb libpmc
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library was written by
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.An "Joseph Koshy"
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.Aq jkoshy@FreeBSD.org .
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MIPS support was added by
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.An "George Neville-Neil"
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.Aq gnn@FreeBSD.org .
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.Sh CAVEATS
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The MIPS code does not yet support sampling.
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