be8d1ddc2e
with the INTR_FILTER-enabled MI code. Basically this consists of
registering an interrupt controller (of which there can be multiple
and optionally different ones either per host-to-foo bridge or shared
amongst host-to-foo bridges in any one machine) along with an interrupt
vector as specific argument for all the interrupt vectors used by a
given host-to-foo bridge (roughly similar to registering interrupt
sources on amd64 and i386), providing functions to enable, clear and
disable the interrupts of the children beneath the bridge.
This also includes:
- No longer entering a critical section in tl0_intr() and tl1_intr()
for executing interrupt handlers but rather let the handlers enter
it themselves so in the case of intr_event_handle() we don't enter
a nested critical section.
- Adding infrastructure for binding delivery of interrupt vectors to
specific CPUs which later on can be interfaced with the code from
amd64/i386 for binding interrupts to specific CPUs.
- Getting rid of the wrapper hack introduced along the lines of the
API changes for INTR_FILTER which as a side-effect caused interrupts
associated with ithread handlers only to get the elevated priority
of those associated with filters ("fast handlers") (this removes the
hack also in the non-INTR_FILTER case).
- Disabling (by not clearing) an interrupt in the interrupt controller
until all associated handlers have been executed, which is crucial
for the typical locking strategy of NIC drivers in order to work
correctly in case of shared interrupts. This was a more or less
theoretical problem on sparc64 though, as shared interrupts are
rather uncommon there except for the on-board SCCs and UARTs.
Note that due to the behavior of at least of some of the interrupt
controllers used on sparc64 an enable+EOI instead of a disable+EOI
approach (as implied by the INTR_FILTER MI code and implemented on
other architectures) is used as the latter can cause lost interrupts
or in the worst case interrupt starvation.
o Correct a typo in sbus_alloc_resource() which caused (pass-through)
allocations to only work down to the grandchildren of the bus, which
wasn't a real problem so far as we don't support any devices which are
great-grandchildren or greater of a U2S bridge, yet.
o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4()
in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid
of some other unneeded members in fhc_softc.
Reviewed by: marcel (earlier version)
Approved by: re (kensmith)
146 lines
7.1 KiB
C
146 lines
7.1 KiB
C
/*-
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* Copyright (c) 1996-1999 Eduardo Horvath
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: sbusreg.h,v 1.7 1999/06/07 05:28:03 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _SPARC64_SBUS_SBUSREG_H_
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#define _SPARC64_SBUS_SBUSREG_H_
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/*
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* Sbus device addresses are obtained from the FORTH PROMs. They come
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* in `absolute' and `relative' address flavors, so we have to handle both.
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* Relative addresses do *not* include the slot number.
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*/
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#define SBUS_BASE 0xf8000000
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#define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off))
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#define SBUS_ABS(a) ((unsigned)(a) >= SBUS_BASE)
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#define SBUS_ABS_TO_SLOT(a) (((a) - SBUS_BASE) >> 25)
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#define SBUS_ABS_TO_OFFSET(a) (((a) - SBUS_BASE) & 0x1ffffff)
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/*
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* Sun4u S-bus definitions. Here's where we deal w/the machine
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* dependencies of sysio.
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*
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* SYSIO implements or is the interface to several things:
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*
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* o The SBUS interface itself
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* o The IOMMU
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* o The DVMA units
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* o The interrupt controller
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* o The counter/timers
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*
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* Since it has registers to control lots of different things
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* as well as several on-board SBUS devices and external SBUS
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* slots scattered throughout its address space, it's a pain.
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*
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* One good point, however, is that all registers are 64-bit.
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*/
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#define SBR_UPA_PORTID 0x0000 /* UPA port ID register */
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#define SBR_UPA_CONFIG 0x0008 /* UPA config register */
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#define SBR_CS 0x0010 /* SYSIO control/status register */
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#define SBR_ECCC 0x0020 /* ECC control register */
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#define SBR_UE_AFS 0x0030 /* Uncorrectable Error AFSR */
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#define SBR_UE_AFA 0x0038 /* Uncorrectable Error AFAR */
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#define SBR_CE_AFS 0x0040 /* Correctable Error AFSR */
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#define SBR_CE_AFA 0x0048 /* Correctable Error AFAR */
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#define SBR_PM_CTL 0x0100 /* Performance monitor control reg */
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#define SBR_PM_COUNT 0x0108 /* Performance monitor counter reg */
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#define SBR_CTL 0x2000 /* SBUS Control Register */
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#define SBR_AFS 0x2010 /* SBUS AFSR */
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#define SBR_AFA 0x2018 /* SBUS AFAR */
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#define SBR_CONFIG0 0x2020 /* SBUS Slot 0 config register */
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#define SBR_CONFIG1 0x2028 /* SBUS Slot 1 config register */
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#define SBR_CONFIG2 0x2030 /* SBUS Slot 2 config register */
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#define SBR_CONFIG3 0x2038 /* SBUS Slot 3 config register */
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#define SBR_CONFIG13 0x2040 /* Slot 13 config register <audio> */
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#define SBR_CONFIG14 0x2048 /* Slot 14 config register <macio> */
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#define SBR_CONFIG15 0x2050 /* Slot 15 config register <slavio> */
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#define SBR_IOMMU 0x2400 /* IOMMU register block */
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#define SBR_STRBUF 0x2800 /* stream buffer register block */
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#define SBR_SLOT0_INT_MAP 0x2c00 /* SBUS slot 0 interrupt map reg */
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#define SBR_SLOT1_INT_MAP 0x2c08 /* SBUS slot 1 interrupt map reg */
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#define SBR_SLOT2_INT_MAP 0x2c10 /* SBUS slot 2 interrupt map reg */
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#define SBR_SLOT3_INT_MAP 0x2c18 /* SBUS slot 3 interrupt map reg */
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#define SBR_INTR_RETRY_TIM 0x2c20 /* interrupt retry timer reg */
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#define SBR_SCSI_INT_MAP 0x3000 /* SCSI interrupt map reg */
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#define SBR_ETHER_INT_MAP 0x3008 /* ethernet interrupt map reg */
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#define SBR_BPP_INT_MAP 0x3010 /* parallel interrupt map reg */
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#define SBR_AUDIO_INT_MAP 0x3018 /* audio interrupt map reg */
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#define SBR_POWER_INT_MAP 0x3020 /* power fail interrupt map reg */
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#define SBR_SKBDMS_INT_MAP 0x3028 /* serial/kbd/mouse interrupt map reg */
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#define SBR_FD_INT_MAP 0x3030 /* floppy interrupt map reg */
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#define SBR_THERM_INT_MAP 0x3038 /* thermal warn interrupt map reg */
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#define SBR_KBD_INT_MAP 0x3040 /* kbd [unused] interrupt map reg */
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#define SBR_MOUSE_INT_MAP 0x3048 /* mouse [unused] interrupt map reg */
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#define SBR_SERIAL_INT_MAP 0x3050 /* second serial interrupt map reg */
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#define SBR_TIMER0_INT_MAP 0x3060 /* timer 0 interrupt map reg */
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#define SBR_TIMER1_INT_MAP 0x3068 /* timer 1 interrupt map reg */
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#define SBR_UE_INT_MAP 0x3070 /* UE interrupt map reg */
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#define SBR_CE_INT_MAP 0x3078 /* CE interrupt map reg */
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#define SBR_ASYNC_INT_MAP 0x3080 /* SBUS error interrupt map reg */
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#define SBR_PWRMGT_INT_MAP 0x3088 /* power mgmt wake interrupt map reg */
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#define SBR_UPAGR_INT_MAP 0x3090 /* UPA graphics interrupt map reg */
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#define SBR_RESERVED_INT_MAP 0x3098 /* reserved interrupt map reg */
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/*
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* Note: clear interrupt 0 registers are not really used
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*/
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#define SBR_SLOT0_INT_CLR 0x3400 /* SBUS slot 0 clear int regs 0..7 */
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#define SBR_SLOT1_INT_CLR 0x3440 /* SBUS slot 1 clear int regs 0..7 */
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#define SBR_SLOT2_INT_CLR 0x3480 /* SBUS slot 2 clear int regs 0..7 */
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#define SBR_SLOT3_INT_CLR 0x34c0 /* SBUS slot 3 clear int regs 0..7 */
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#define SBR_SCSI_INT_CLR 0x3800 /* SCSI clear int reg */
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#define SBR_ETHER_INT_CLR 0x3808 /* ethernet clear int reg */
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#define SBR_BPP_INT_CLR 0x3810 /* parallel clear int reg */
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#define SBR_AUDIO_INT_CLR 0x3818 /* audio clear int reg */
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#define SBR_POWER_INT_CLR 0x3820 /* power fail clear int reg */
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#define SBR_SKBDMS_INT_CLR 0x3828 /* serial/kbd/mouse clear int reg */
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#define SBR_FD_INT_CLR 0x3830 /* floppy clear int reg */
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#define SBR_THERM_INT_CLR 0x3838 /* thermal warn clear int reg */
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#define SBR_KBD_INT_CLR 0x3840 /* kbd [unused] clear int reg */
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#define SBR_MOUSE_INT_CLR 0x3848 /* mouse [unused] clear int reg */
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#define SBR_SERIAL_INT_CLR 0x3850 /* second serial clear int reg */
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#define SBR_TIMER0_INT_CLR 0x3860 /* timer 0 clear int reg */
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#define SBR_TIMER1_INT_CLR 0x3868 /* timer 1 clear int reg */
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#define SBR_UE_INT_CLR 0x3870 /* UE clear int reg */
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#define SBR_CE_INT_CLR 0x3878 /* CE clear int reg */
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#define SBR_ASYNC_INT_CLR 0x3880 /* SBUS error clr interrupt reg */
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#define SBR_PWRMGT_INT_CLR 0x3888 /* power mgmt wake clr interrupt reg */
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#define SBR_TC0 0x3c00 /* timer/counter 0 */
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#define SBR_TC1 0x3c10 /* timer/counter 1 */
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#define SBR_IOMMU_SVADIAG 0x4400 /* SBUS virtual addr diag reg */
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#define SBR_IOMMU_QUEUE_DIAG 0x4500 /* IOMMU LRU queue diag 0..15 */
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#define SBR_IOMMU_TLB_TAG_DIAG 0x4580 /* TLB tag diag 0..15 */
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#define SBR_IOMMU_TLB_DATA_DIAG 0x4600 /* TLB data RAM diag 0..31 */
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#define SBR_INT_DIAG 0x4800 /* SBUS int state diag reg */
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#define SBR_OBIO_DIAG 0x4808 /* OBIO and misc int state diag reg */
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#define SBR_STRBUF_DIAG 0x5000 /* Streaming buffer diag regs */
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/* INO defines */
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#define SBUS_MAX_INO 0x3f
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/* Width of the physical addresses the IOMMU translates to */
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#define SBUS_IOMMU_BITS 41
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#endif /* _SPARC64_SBUS_SBUSREG_H_ */
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