387 lines
19 KiB
C
387 lines
19 KiB
C
/*******************************************************************************
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Copyright (c) 2001-2002 Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms of the Software, with or
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without modification, are permitted provided that the following conditions
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are met:
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1. Redistributions of source code of the Software may retain the above
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copyright notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form of the Software may reproduce the above
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copyright notice, this list of conditions and the following disclaimer
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in the documentation and/or other materials provided with the
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distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors shall be used to endorse or promote products derived from
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this Software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS CONTRIBUTORS BE LIABLE
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FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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SUCH DAMAGE.
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*******************************************************************************/
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/*$FreeBSD$*/
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/* if_em_phy.h
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* Structures, enums, and macros for the PHY
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*/
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#ifndef _EM_PHY_H_
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#define _EM_PHY_H_
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#include <dev/em/if_em_osdep.h>
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/* PHY status info structure and supporting enums */
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typedef enum {
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em_cable_length_50 = 0,
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em_cable_length_50_80,
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em_cable_length_80_110,
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em_cable_length_110_140,
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em_cable_length_140,
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em_cable_length_undefined = 0xFF
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} em_cable_length;
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typedef enum {
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em_10bt_ext_dist_enable_normal = 0,
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em_10bt_ext_dist_enable_lower,
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em_10bt_ext_dist_enable_undefined = 0xFF
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} em_10bt_ext_dist_enable;
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typedef enum {
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em_rev_polarity_normal = 0,
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em_rev_polarity_reversed,
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em_rev_polarity_undefined = 0xFF
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} em_rev_polarity;
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typedef enum {
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em_polarity_reversal_enabled = 0,
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em_polarity_reversal_disabled,
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em_polarity_reversal_undefined = 0xFF
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} em_polarity_reversal;
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typedef enum {
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em_down_no_idle_no_detect = 0,
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em_down_no_idle_detect,
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em_down_no_idle_undefined = 0xFF
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} em_down_no_idle;
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typedef enum {
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em_auto_x_mode_manual_mdi = 0,
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em_auto_x_mode_manual_mdix,
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em_auto_x_mode_auto1,
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em_auto_x_mode_auto2,
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em_auto_x_mode_undefined = 0xFF
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} em_auto_x_mode;
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typedef enum {
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em_1000t_rx_status_not_ok = 0,
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em_1000t_rx_status_ok,
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em_1000t_rx_status_undefined = 0xFF
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} em_1000t_rx_status;
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struct em_phy_info {
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em_cable_length cable_length;
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em_10bt_ext_dist_enable extended_10bt_distance;
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em_rev_polarity cable_polarity;
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em_polarity_reversal polarity_correction;
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em_down_no_idle link_reset;
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em_auto_x_mode mdix_mode;
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em_1000t_rx_status local_rx;
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em_1000t_rx_status remote_rx;
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};
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struct em_phy_stats {
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uint32_t idle_errors;
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uint32_t receive_errors;
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};
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/* Function Prototypes */
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uint16_t em_read_phy_reg(struct em_shared_adapter *shared, uint32_t reg_addr);
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void em_write_phy_reg(struct em_shared_adapter *shared, uint32_t reg_addr, uint16_t data);
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void em_phy_hw_reset(struct em_shared_adapter *shared);
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boolean_t em_phy_reset(struct em_shared_adapter *shared);
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boolean_t em_phy_setup(struct em_shared_adapter *shared, uint32_t ctrl_reg);
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boolean_t em_phy_setup_autoneg(struct em_shared_adapter *shared);
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void em_config_mac_to_phy(struct em_shared_adapter *shared, uint16_t mii_reg);
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void em_config_collision_dist(struct em_shared_adapter *shared);
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void em_display_mii(struct em_shared_adapter *shared);
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boolean_t em_detect_gig_phy(struct em_shared_adapter *shared);
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void em_phy_reset_dsp(struct em_shared_adapter *shared);
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boolean_t em_wait_autoneg(struct em_shared_adapter *shared);
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boolean_t em_phy_get_info(struct em_shared_adapter *shared, struct em_phy_info *phy_status_info);
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boolean_t em_validate_mdi_setting(struct em_shared_adapter *shared);
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/* Bit definitions for the Management Data IO (MDIO) and Management Data
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* Clock (MDC) pins in the Device Control Register.
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*/
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#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
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#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
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#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
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#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
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#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
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#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
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#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
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#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
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/* PHY 1000 MII Register/Bit Definitions */
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/* PHY Registers defined by IEEE */
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#define PHY_CTRL 0x00 /* Control Register */
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#define PHY_STATUS 0x01 /* Status Regiser */
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#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
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#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
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#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
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#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
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#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
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#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
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#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
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#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
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#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
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#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
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/* M88E1000 Specific Registers */
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#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
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#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
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#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
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#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
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#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
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#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
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#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
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/* PHY Control Register */
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#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
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#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
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#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
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#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
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#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
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#define MII_CR_POWER_DOWN 0x0800 /* Power down */
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#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
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#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
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#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
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#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
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/* PHY Status Register */
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#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
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#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
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#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
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#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
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#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
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#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
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#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
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#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
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#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
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#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
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#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
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#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
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#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
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#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
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#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
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/* Autoneg Advertisement Register */
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#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
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#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
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#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
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#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
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#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
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#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
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#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
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#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
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#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
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#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
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/* Link Partner Ability Register (Base Page) */
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#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
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#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
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#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
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#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
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#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
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#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
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#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
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#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
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#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
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#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
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#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
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/* Autoneg Expansion Register */
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#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
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#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
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#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
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#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
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#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
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/* Next Page TX Register */
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#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
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#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
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* of different NP
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*/
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#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
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* 0 = cannot comply with msg
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*/
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#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
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#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
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* 0 = sending last NP
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*/
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/* Link Partner Next Page Register */
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#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
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#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
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* of different NP
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*/
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#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
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* 0 = cannot comply with msg
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*/
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#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
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#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
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#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
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* 0 = sending last NP
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*/
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/* 1000BASE-T Control Register */
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#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
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#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
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#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
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#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
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/* 0=DTE device */
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#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
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/* 0=Configure PHY as Slave */
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#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
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/* 0=Automatic Master/Slave config */
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#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
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#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
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#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
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#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
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#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
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/* 1000BASE-T Status Register */
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#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
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#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
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#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
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#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
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#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
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#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
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#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
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#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
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#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
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#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
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/* Extended Status Register */
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#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
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#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
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#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
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#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
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#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
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#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
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#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
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/* (0=enable, 1=disable) */
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/* M88E1000 PHY Specific Control Register */
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#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
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#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
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#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
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#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
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* 0=CLK125 toggling
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*/
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#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
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/* Manual MDI configuration */
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#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
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#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
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* 100BASE-TX/10BASE-T:
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* MDI Mode
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*/
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#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
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* all speeds.
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*/
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#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
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/* 1=Enable Extended 10BASE-T distance
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* (Lower 10BASE-T RX Threshold)
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* 0=Normal 10BASE-T RX Threshold */
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#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
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/* 1=5-Bit interface in 100BASE-TX
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* 0=MII interface in 100BASE-TX */
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#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
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#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
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#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
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#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
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#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
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#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
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/* M88E1000 PHY Specific Status Register */
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#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
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#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
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#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
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#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
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* 3=110-140M;4=>140M */
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#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
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#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
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#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
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#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
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#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
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#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
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#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
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#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
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#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
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#define M88E1000_PSSR_MDIX_SHIFT 6
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#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
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/* M88E1000 Extended PHY Specific Control Register */
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#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
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#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
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* Will assert lost lock and bring
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* link down if idle not seen
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* within 1ms in 1000BASE-T
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*/
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#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
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#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
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#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
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#define M88E1000_EPSCR_DOWN_NO_IDLE_SHIFT 15
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/* Bit definitions for valid PHY IDs. */
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#define M88E1000_12_PHY_ID 0x01410C50
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#define M88E1000_14_PHY_ID 0x01410C40
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#define M88E1000_I_PHY_ID 0x01410C30
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#define M88E1011_I_PHY_ID 0x01410C20
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/* Miscellaneous PHY bit definitions. */
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#define PHY_PREAMBLE 0xFFFFFFFF
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#define PHY_SOF 0x01
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#define PHY_OP_READ 0x02
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#define PHY_OP_WRITE 0x01
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#define PHY_TURNAROUND 0x02
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#define PHY_PREAMBLE_SIZE 32
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#define MII_CR_SPEED_1000 0x0040
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#define MII_CR_SPEED_100 0x2000
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#define MII_CR_SPEED_10 0x0000
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#define E1000_PHY_ADDRESS 0x01
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#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
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#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
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#define PHY_REVISION_MASK 0xFFFFFFF0
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#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
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#define REG4_SPEED_MASK 0x01E0
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#define REG9_SPEED_MASK 0x0300
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#define ADVERTISE_10_HALF 0x0001
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#define ADVERTISE_10_FULL 0x0002
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#define ADVERTISE_100_HALF 0x0004
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#define ADVERTISE_100_FULL 0x0008
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#define ADVERTISE_1000_HALF 0x0010
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#define ADVERTISE_1000_FULL 0x0020
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#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
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#endif /* _EM_PHY_H_ */
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