86bce74937
FDT-enabled targets were broken after r238043 that relies on device up the hierarchy to properly setup interrupt. nexus device for ARM platforms did job only partially: setting handler but not unmasking interrupt. Unmasking was performed by platform code. Reviewed by: andrew@
799 lines
21 KiB
C
799 lines
21 KiB
C
/* $NetBSD: s3c2410.c,v 1.4 2003/08/27 03:46:05 bsh Exp $ */
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/*
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* Copyright (c) 2003 Genetec corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corporation may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/reboot.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/cpufunc.h>
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#include <machine/intr.h>
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#include <arm/s3c2xx0/s3c2410reg.h>
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#include <arm/s3c2xx0/s3c2440reg.h>
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#include <arm/s3c2xx0/s3c24x0var.h>
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#include <sys/rman.h>
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#define S3C2XX0_XTAL_CLK 12000000
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#define IPL_LEVELS 13
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u_int irqmasks[IPL_LEVELS];
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static struct {
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uint32_t idcode;
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const char *name;
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s3c2xx0_cpu cpu;
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} s3c2x0_cpu_id[] = {
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{ CHIPID_S3C2410A, "S3C2410A", CPU_S3C2410 },
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{ CHIPID_S3C2440A, "S3C2440A", CPU_S3C2440 },
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{ CHIPID_S3C2442B, "S3C2442B", CPU_S3C2440 },
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{ 0, NULL }
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};
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static struct {
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const char *name;
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int prio;
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int unit;
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struct {
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int type;
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u_long start;
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u_long count;
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} res[2];
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} s3c24x0_children[] = {
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{ "rtc", 0, -1, {
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{ SYS_RES_IOPORT, S3C24X0_RTC_PA_BASE, S3C24X0_RTC_SIZE },
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{ 0 },
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} },
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{ "timer", 0, -1, { { 0 }, } },
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{ "uart", 1, 0, {
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{ SYS_RES_IRQ, S3C24X0_INT_UART0, 1 },
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{ SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(0),
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S3C24X0_UART_BASE(1) - S3C24X0_UART_BASE(0) },
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} },
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{ "uart", 1, 1, {
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{ SYS_RES_IRQ, S3C24X0_INT_UART1, 1 },
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{ SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(1),
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S3C24X0_UART_BASE(2) - S3C24X0_UART_BASE(1) },
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} },
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{ "uart", 1, 2, {
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{ SYS_RES_IRQ, S3C24X0_INT_UART2, 1 },
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{ SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(2),
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S3C24X0_UART_BASE(3) - S3C24X0_UART_BASE(2) },
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} },
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{ "ohci", 0, -1, {
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{ SYS_RES_IRQ, S3C24X0_INT_USBH, 0 },
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{ SYS_RES_IOPORT, S3C24X0_USBHC_PA_BASE, S3C24X0_USBHC_SIZE },
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} },
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{ NULL },
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};
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/* prototypes */
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static device_t s3c24x0_add_child(device_t, int, const char *, int);
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static int s3c24x0_probe(device_t);
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static int s3c24x0_attach(device_t);
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static void s3c24x0_identify(driver_t *, device_t);
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static int s3c24x0_setup_intr(device_t, device_t, struct resource *, int,
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driver_filter_t *, driver_intr_t *, void *, void **);
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static int s3c24x0_teardown_intr(device_t, device_t, struct resource *,
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void *);
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static int s3c24x0_config_intr(device_t, int, enum intr_trigger,
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enum intr_polarity);
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static struct resource *s3c24x0_alloc_resource(device_t, device_t, int, int *,
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u_long, u_long, u_long, u_int);
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static int s3c24x0_activate_resource(device_t, device_t, int, int,
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struct resource *);
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static int s3c24x0_release_resource(device_t, device_t, int, int,
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struct resource *);
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static struct resource_list *s3c24x0_get_resource_list(device_t, device_t);
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static void s3c24x0_identify_cpu(device_t);
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static device_method_t s3c24x0_methods[] = {
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DEVMETHOD(device_probe, s3c24x0_probe),
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DEVMETHOD(device_attach, s3c24x0_attach),
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DEVMETHOD(device_identify, s3c24x0_identify),
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DEVMETHOD(bus_setup_intr, s3c24x0_setup_intr),
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DEVMETHOD(bus_teardown_intr, s3c24x0_teardown_intr),
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DEVMETHOD(bus_config_intr, s3c24x0_config_intr),
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DEVMETHOD(bus_alloc_resource, s3c24x0_alloc_resource),
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DEVMETHOD(bus_activate_resource, s3c24x0_activate_resource),
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DEVMETHOD(bus_release_resource, s3c24x0_release_resource),
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DEVMETHOD(bus_get_resource_list,s3c24x0_get_resource_list),
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DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
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DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
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{0, 0},
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};
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static driver_t s3c24x0_driver = {
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"s3c24x0",
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s3c24x0_methods,
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sizeof(struct s3c24x0_softc),
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};
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static devclass_t s3c24x0_devclass;
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DRIVER_MODULE(s3c24x0, nexus, s3c24x0_driver, s3c24x0_devclass, 0, 0);
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struct s3c2xx0_softc *s3c2xx0_softc = NULL;
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static device_t
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s3c24x0_add_child(device_t bus, int prio, const char *name, int unit)
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{
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device_t child;
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struct s3c2xx0_ivar *ivar;
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child = device_add_child_ordered(bus, prio, name, unit);
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if (child == NULL)
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return (NULL);
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ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO);
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if (ivar == NULL) {
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device_delete_child(bus, child);
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printf("Can't add alloc ivar\n");
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return (NULL);
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}
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device_set_ivars(child, ivar);
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resource_list_init(&ivar->resources);
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return (child);
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}
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static void
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s3c24x0_enable_ext_intr(unsigned int irq)
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{
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uint32_t reg, value;
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int offset;
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if (irq <= 7) {
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reg = GPIO_PFCON;
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offset = irq * 2;
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} else if (irq <= 23) {
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reg = GPIO_PGCON;
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offset = (irq - 8) * 2;
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} else
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return;
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/* Make the pin an interrupt source */
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value = bus_space_read_4(s3c2xx0_softc->sc_iot,
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s3c2xx0_softc->sc_gpio_ioh, reg);
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value &= ~(3 << offset);
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value |= 2 << offset;
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bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
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reg, value);
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}
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static int
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s3c24x0_setup_intr(device_t dev, device_t child,
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struct resource *ires, int flags, driver_filter_t *filt,
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driver_intr_t *intr, void *arg, void **cookiep)
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{
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int error, irq;
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error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt,
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intr, arg, cookiep);
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if (error != 0)
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return (error);
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for (irq = rman_get_start(ires); irq <= rman_get_end(ires); irq++) {
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if (irq >= S3C24X0_EXTIRQ_MIN && irq <= S3C24X0_EXTIRQ_MAX) {
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/* Enable the external interrupt pin */
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s3c24x0_enable_ext_intr(irq - S3C24X0_EXTIRQ_MIN);
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}
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}
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return (0);
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}
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static int
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s3c24x0_teardown_intr(device_t dev, device_t child, struct resource *res,
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void *cookie)
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{
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return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
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}
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static int
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s3c24x0_config_intr(device_t dev, int irq, enum intr_trigger trig,
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enum intr_polarity pol)
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{
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uint32_t mask, reg, value;
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int offset;
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/* Only external interrupts can be configured */
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if (irq < S3C24X0_EXTIRQ_MIN || irq > S3C24X0_EXTIRQ_MAX)
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return (EINVAL);
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/* There is no standard trigger or polarity for the bus */
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if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
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return (EINVAL);
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irq -= S3C24X0_EXTIRQ_MIN;
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/* Get the bits to set */
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mask = 0;
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if (pol == INTR_POLARITY_LOW) {
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mask = 2;
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} else if (pol == INTR_POLARITY_HIGH) {
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mask = 4;
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}
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if (trig == INTR_TRIGGER_LEVEL) {
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mask >>= 2;
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}
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/* Get the register to set */
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if (irq <= 7) {
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reg = GPIO_EXTINT(0);
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offset = irq * 4;
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} else if (irq <= 15) {
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reg = GPIO_EXTINT(1);
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offset = (irq - 8) * 4;
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} else if (irq <= 23) {
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reg = GPIO_EXTINT(2);
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offset = (irq - 16) * 4;
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} else {
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return (EINVAL);
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}
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/* Set the new signaling method */
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value = bus_space_read_4(s3c2xx0_softc->sc_iot,
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s3c2xx0_softc->sc_gpio_ioh, reg);
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value &= ~(7 << offset);
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value |= mask << offset;
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bus_space_write_4(s3c2xx0_softc->sc_iot,
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s3c2xx0_softc->sc_gpio_ioh, reg, value);
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return (0);
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}
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static struct resource *
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s3c24x0_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct resource_list_entry *rle;
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struct s3c2xx0_ivar *ivar = device_get_ivars(child);
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struct resource_list *rl = &ivar->resources;
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struct resource *res = NULL;
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if (device_get_parent(child) != bus)
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return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
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type, rid, start, end, count, flags));
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rle = resource_list_find(rl, type, *rid);
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if (rle != NULL) {
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/* There is a resource list. Use it */
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if (rle->res)
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panic("Resource rid %d type %d already in use", *rid,
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type);
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if (start == 0UL && end == ~0UL) {
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start = rle->start;
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count = ulmax(count, rle->count);
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end = ulmax(rle->end, start + count - 1);
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}
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/*
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* When allocating an irq with children irq's really
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* allocate the children as it is those we are interested
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* in receiving, not the parent.
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*/
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if (type == SYS_RES_IRQ && start == end) {
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switch (start) {
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case S3C24X0_INT_ADCTC:
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start = S3C24X0_INT_TC;
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end = S3C24X0_INT_ADC;
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break;
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#ifdef S3C2440_INT_CAM
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case S3C2440_INT_CAM:
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start = S3C2440_INT_CAM_C;
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end = S3C2440_INT_CAM_P;
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break;
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#endif
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default:
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break;
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}
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count = end - start + 1;
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}
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}
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switch (type) {
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case SYS_RES_IRQ:
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res = rman_reserve_resource(
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&s3c2xx0_softc->s3c2xx0_irq_rman, start, end,
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count, flags, child);
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break;
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case SYS_RES_IOPORT:
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case SYS_RES_MEMORY:
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res = rman_reserve_resource(
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&s3c2xx0_softc->s3c2xx0_mem_rman,
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start, end, count, flags, child);
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if (res == NULL)
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panic("Unable to map address space %#lX-%#lX", start,
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end);
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rman_set_bustag(res, &s3c2xx0_bs_tag);
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rman_set_bushandle(res, start);
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if (flags & RF_ACTIVE) {
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if (bus_activate_resource(child, type, *rid, res)) {
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rman_release_resource(res);
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return (NULL);
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}
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}
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break;
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}
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if (res != NULL) {
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rman_set_rid(res, *rid);
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if (rle != NULL) {
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rle->res = res;
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rle->start = rman_get_start(res);
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rle->end = rman_get_end(res);
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rle->count = count;
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}
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}
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return (res);
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}
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static int
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s3c24x0_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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bus_space_handle_t p;
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int error;
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if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
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error = bus_space_map(rman_get_bustag(r),
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rman_get_bushandle(r), rman_get_size(r), 0, &p);
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if (error)
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return (error);
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rman_set_bushandle(r, p);
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}
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return (rman_activate_resource(r));
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}
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static int
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s3c24x0_release_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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struct s3c2xx0_ivar *ivar = device_get_ivars(child);
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struct resource_list *rl = &ivar->resources;
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struct resource_list_entry *rle;
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if (rl == NULL)
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return (EINVAL);
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rle = resource_list_find(rl, type, rid);
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if (rle == NULL)
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return (EINVAL);
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rman_release_resource(r);
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rle->res = NULL;
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return 0;
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}
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static struct resource_list *
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s3c24x0_get_resource_list(device_t dev, device_t child)
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{
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struct s3c2xx0_ivar *ivar;
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ivar = device_get_ivars(child);
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return (&(ivar->resources));
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}
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void
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s3c24x0_identify(driver_t *driver, device_t parent)
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{
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BUS_ADD_CHILD(parent, 0, "s3c24x0", 0);
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}
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int
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s3c24x0_probe(device_t dev)
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{
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return 0;
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}
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int
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s3c24x0_attach(device_t dev)
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{
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struct s3c24x0_softc *sc = device_get_softc(dev);
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bus_space_tag_t iot;
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device_t child;
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unsigned int i, j;
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u_long irqmax;
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s3c2xx0_softc = &(sc->sc_sx);
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sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
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s3c2xx0_softc->s3c2xx0_irq_rman.rm_type = RMAN_ARRAY;
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s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C24X0 IRQs";
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s3c2xx0_softc->s3c2xx0_mem_rman.rm_type = RMAN_ARRAY;
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s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C24X0 Device Registers";
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/* Manage the registor memory space */
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if ((rman_init(&s3c2xx0_softc->s3c2xx0_mem_rman) != 0) ||
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(rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
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S3C24X0_DEV_VA_OFFSET,
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S3C24X0_DEV_VA_OFFSET + S3C24X0_DEV_VA_SIZE) != 0) ||
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(rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
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S3C24X0_DEV_START, S3C24X0_DEV_STOP) != 0))
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panic("s3c24x0_attach: failed to set up register rman");
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|
/* These are needed for things without a proper device to attach to */
|
|
sc->sc_sx.sc_intctl_ioh = S3C24X0_INTCTL_BASE;
|
|
sc->sc_sx.sc_gpio_ioh = S3C24X0_GPIO_BASE;
|
|
sc->sc_sx.sc_clkman_ioh = S3C24X0_CLKMAN_BASE;
|
|
sc->sc_sx.sc_wdt_ioh = S3C24X0_WDT_BASE;
|
|
sc->sc_timer_ioh = S3C24X0_TIMER_BASE;
|
|
|
|
/*
|
|
* Identify the CPU
|
|
*/
|
|
s3c24x0_identify_cpu(dev);
|
|
|
|
/*
|
|
* Manage the interrupt space.
|
|
* We need to put this after s3c24x0_identify_cpu as the avaliable
|
|
* interrupts change depending on which CPU we have.
|
|
*/
|
|
if (sc->sc_sx.sc_cpu == CPU_S3C2410)
|
|
irqmax = S3C2410_SUBIRQ_MAX;
|
|
else
|
|
irqmax = S3C2440_SUBIRQ_MAX;
|
|
if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 ||
|
|
rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0,
|
|
irqmax) != 0 ||
|
|
rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman,
|
|
S3C24X0_EXTIRQ_MIN, S3C24X0_EXTIRQ_MAX))
|
|
panic("s3c24x0_attach: failed to set up IRQ rman");
|
|
|
|
/* calculate current clock frequency */
|
|
s3c24x0_clock_freq(&sc->sc_sx);
|
|
device_printf(dev, "fclk %d MHz hclk %d MHz pclk %d MHz\n",
|
|
sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
|
|
sc->sc_sx.sc_pclk / 1000000);
|
|
|
|
/*
|
|
* Attach children devices
|
|
*/
|
|
|
|
for (i = 0; s3c24x0_children[i].name != NULL; i++) {
|
|
child = s3c24x0_add_child(dev, s3c24x0_children[i].prio,
|
|
s3c24x0_children[i].name, s3c24x0_children[i].unit);
|
|
for (j = 0; j < sizeof(s3c24x0_children[i].res) /
|
|
sizeof(s3c24x0_children[i].res[0]) &&
|
|
s3c24x0_children[i].res[j].type != 0; j++) {
|
|
bus_set_resource(child,
|
|
s3c24x0_children[i].res[j].type, 0,
|
|
s3c24x0_children[i].res[j].start,
|
|
s3c24x0_children[i].res[j].count);
|
|
}
|
|
}
|
|
|
|
bus_generic_probe(dev);
|
|
bus_generic_attach(dev);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
s3c24x0_identify_cpu(device_t dev)
|
|
{
|
|
struct s3c24x0_softc *sc = device_get_softc(dev);
|
|
uint32_t idcode;
|
|
int i;
|
|
|
|
idcode = bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_gpio_ioh,
|
|
GPIO_GSTATUS1);
|
|
|
|
for (i = 0; s3c2x0_cpu_id[i].name != NULL; i++) {
|
|
if (s3c2x0_cpu_id[i].idcode == idcode)
|
|
break;
|
|
}
|
|
if (s3c2x0_cpu_id[i].name == NULL)
|
|
panic("Unknown CPU detected ((Chip ID: %#X)", idcode);
|
|
device_printf(dev, "Found %s CPU (Chip ID: %#X)\n",
|
|
s3c2x0_cpu_id[i].name, idcode);
|
|
sc->sc_sx.sc_cpu = s3c2x0_cpu_id[i].cpu;
|
|
}
|
|
|
|
/*
|
|
* fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register.
|
|
*
|
|
* s3c24{1,4}0_clock_freq2() is meant to be called from kernel startup routines.
|
|
* s3c24x0_clock_freq() is for after kernel initialization is done.
|
|
*
|
|
* Because they can be called before bus_space is available we need to use
|
|
* volatile pointers rather than bus_space_read.
|
|
*/
|
|
void
|
|
s3c2410_clock_freq2(vm_offset_t clkman_base, int *fclk, int *hclk, int *pclk)
|
|
{
|
|
uint32_t pllcon, divn;
|
|
unsigned int mdiv, pdiv, sdiv;
|
|
unsigned int f, h, p;
|
|
|
|
pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON);
|
|
divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
|
|
|
|
mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
|
|
pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
|
|
sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
|
|
|
|
f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv));
|
|
h = f;
|
|
if (divn & S3C2410_CLKDIVN_HDIVN)
|
|
h /= 2;
|
|
p = h;
|
|
if (divn & CLKDIVN_PDIVN)
|
|
p /= 2;
|
|
|
|
if (fclk) *fclk = f;
|
|
if (hclk) *hclk = h;
|
|
if (pclk) *pclk = p;
|
|
}
|
|
|
|
void
|
|
s3c2440_clock_freq2(vm_offset_t clkman_base, int *fclk, int *hclk, int *pclk)
|
|
{
|
|
uint32_t pllcon, divn, camdivn;
|
|
unsigned int mdiv, pdiv, sdiv;
|
|
unsigned int f, h, p;
|
|
|
|
pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON);
|
|
divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
|
|
camdivn = *(volatile uint32_t *)(clkman_base + S3C2440_CLKMAN_CAMDIVN);
|
|
|
|
mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
|
|
pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
|
|
sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
|
|
|
|
f = (2 * (mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv));
|
|
h = f;
|
|
switch((divn >> 1) & 3) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
h /= 2;
|
|
break;
|
|
case 2:
|
|
if ((camdivn & S3C2440_CAMDIVN_HCLK4_HALF) ==
|
|
S3C2440_CAMDIVN_HCLK4_HALF)
|
|
h /= 8;
|
|
else
|
|
h /= 4;
|
|
break;
|
|
case 3:
|
|
if ((camdivn & S3C2440_CAMDIVN_HCLK3_HALF) ==
|
|
S3C2440_CAMDIVN_HCLK3_HALF)
|
|
h /= 6;
|
|
else
|
|
h /= 3;
|
|
break;
|
|
}
|
|
p = h;
|
|
if (divn & CLKDIVN_PDIVN)
|
|
p /= 2;
|
|
|
|
if (fclk) *fclk = f;
|
|
if (hclk) *hclk = h;
|
|
if (pclk) *pclk = p;
|
|
}
|
|
|
|
void
|
|
s3c24x0_clock_freq(struct s3c2xx0_softc *sc)
|
|
{
|
|
vm_offset_t va;
|
|
|
|
va = sc->sc_clkman_ioh;
|
|
switch(sc->sc_cpu) {
|
|
case CPU_S3C2410:
|
|
s3c2410_clock_freq2(va, &sc->sc_fclk, &sc->sc_hclk,
|
|
&sc->sc_pclk);
|
|
break;
|
|
case CPU_S3C2440:
|
|
s3c2440_clock_freq2(va, &sc->sc_fclk, &sc->sc_hclk,
|
|
&sc->sc_pclk);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void
|
|
cpu_reset(void)
|
|
{
|
|
(void) disable_interrupts(I32_bit|F32_bit);
|
|
|
|
bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_wdt_ioh, WDT_WTCON,
|
|
WTCON_ENABLE | WTCON_CLKSEL_16 | WTCON_ENRST);
|
|
for(;;);
|
|
}
|
|
|
|
void
|
|
s3c24x0_sleep(int mode __unused)
|
|
{
|
|
int reg;
|
|
|
|
reg = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh,
|
|
CLKMAN_CLKCON);
|
|
bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh,
|
|
CLKMAN_CLKCON, reg | CLKCON_IDLE);
|
|
}
|
|
|
|
|
|
int
|
|
arm_get_next_irq(int last __unused)
|
|
{
|
|
uint32_t intpnd;
|
|
int irq, subirq;
|
|
|
|
if ((irq = bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTOFFSET)) != 0) {
|
|
|
|
/* Clear the pending bit */
|
|
intpnd = bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTPND);
|
|
bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh,
|
|
INTCTL_SRCPND, intpnd);
|
|
bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh,
|
|
INTCTL_INTPND, intpnd);
|
|
|
|
switch (irq) {
|
|
case S3C24X0_INT_ADCTC:
|
|
case S3C24X0_INT_UART0:
|
|
case S3C24X0_INT_UART1:
|
|
case S3C24X0_INT_UART2:
|
|
/* Find the sub IRQ */
|
|
subirq = 0x7ff;
|
|
subirq &= bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND);
|
|
subirq &= ~(bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK));
|
|
if (subirq == 0)
|
|
return (irq);
|
|
|
|
subirq = ffs(subirq) - 1;
|
|
|
|
/* Clear the sub irq pending bit */
|
|
bus_space_write_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND,
|
|
(1 << subirq));
|
|
|
|
/*
|
|
* Return the parent IRQ for UART
|
|
* as it is all we ever need
|
|
*/
|
|
if (subirq <= 8)
|
|
return (irq);
|
|
|
|
return (S3C24X0_SUBIRQ_MIN + subirq);
|
|
|
|
case S3C24X0_INT_0:
|
|
case S3C24X0_INT_1:
|
|
case S3C24X0_INT_2:
|
|
case S3C24X0_INT_3:
|
|
/* There is a 1:1 mapping to the IRQ we are handling */
|
|
return S3C24X0_INT_EXT(irq);
|
|
|
|
case S3C24X0_INT_4_7:
|
|
case S3C24X0_INT_8_23:
|
|
/* Find the external interrupt being called */
|
|
subirq = 0x7fffff;
|
|
subirq &= bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND);
|
|
subirq &= ~bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
|
|
if (subirq == 0)
|
|
return (irq);
|
|
|
|
subirq = ffs(subirq) - 1;
|
|
|
|
/* Clear the external irq pending bit */
|
|
bus_space_write_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND,
|
|
(1 << subirq));
|
|
|
|
return S3C24X0_INT_EXT(subirq);
|
|
}
|
|
|
|
return (irq);
|
|
}
|
|
return (-1);
|
|
}
|
|
|
|
void
|
|
arm_mask_irq(uintptr_t irq)
|
|
{
|
|
u_int32_t mask;
|
|
|
|
if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) {
|
|
/* External interrupt 0..3 are directly mapped to irq 0..3 */
|
|
irq -= S3C24X0_EXTIRQ_MIN;
|
|
}
|
|
if (irq < S3C24X0_SUBIRQ_MIN) {
|
|
mask = bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
|
|
mask |= (1 << irq);
|
|
bus_space_write_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
|
|
} else if (irq < S3C24X0_EXTIRQ_MIN) {
|
|
mask = bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
|
|
mask |= (1 << (irq - S3C24X0_SUBIRQ_MIN));
|
|
bus_space_write_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
|
|
} else {
|
|
mask = bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
|
|
mask |= (1 << (irq - S3C24X0_EXTIRQ_MIN));
|
|
bus_space_write_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask);
|
|
}
|
|
}
|
|
|
|
void
|
|
arm_unmask_irq(uintptr_t irq)
|
|
{
|
|
u_int32_t mask;
|
|
|
|
if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) {
|
|
/* External interrupt 0..3 are directly mapped to irq 0..3 */
|
|
irq -= S3C24X0_EXTIRQ_MIN;
|
|
}
|
|
if (irq < S3C24X0_SUBIRQ_MIN) {
|
|
mask = bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
|
|
mask &= ~(1 << irq);
|
|
bus_space_write_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
|
|
} else if (irq < S3C24X0_EXTIRQ_MIN) {
|
|
mask = bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
|
|
mask &= ~(1 << (irq - S3C24X0_SUBIRQ_MIN));
|
|
bus_space_write_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
|
|
} else {
|
|
mask = bus_space_read_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
|
|
mask &= ~(1 << (irq - S3C24X0_EXTIRQ_MIN));
|
|
bus_space_write_4(&s3c2xx0_bs_tag,
|
|
s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask);
|
|
}
|
|
}
|