143 lines
4.8 KiB
C
143 lines
4.8 KiB
C
/*-
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* Copyright (c) 2012 M. Warner Losh. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91board.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91rm9200var.h>
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#include <arm/at91/at91_pioreg.h>
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#include <arm/at91/at91_piovar.h>
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/*
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* The AT91RM9200 uses the same silicon for both the BGA and PQFP
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* packages. There's no documented way to detect this at runtime,
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* so we require the board code to register what type of SoC is on the
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* board in question. The pinouts are not quite compatible, and we
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* use this information to cope with the slight differences.
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*/
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void
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at91rm9200_set_subtype(enum at91_soc_subtype st)
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{
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switch (st) {
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case AT91_ST_RM9200_BGA:
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case AT91_ST_RM9200_PQFP:
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soc_info.subtype = st;
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break;
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default:
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panic("Bad SoC subtype %d for at91rm9200_set_subtype.", st);
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break;
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}
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}
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void
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at91rm9200_config_uart(unsigned devid, unsigned unit, unsigned pinmask)
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{
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/*
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* Since the USART supports RS-485 multidrop mode, it allows the
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* TX pins to float. However, for RS-232 operations, we don't want
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* these pins to float. Instead, they should be pulled up to avoid
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* mismatches. Linux does something similar when it configures the
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* TX lines. This implies that we also allow the RX lines to float
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* rather than be in the state they are left in by the boot loader.
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* Since they are input pins, I think that this is the right thing
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* to do.
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*/
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/*
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* Current boards supported don't need the extras, but they should be
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* implemented. But that should wait until the new pin api goes in.
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*/
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switch (devid) {
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case AT91_ID_DBGU:
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA30, 0); /* DRXD */
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA31, 1); /* DTXD */
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break;
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case AT91RM9200_ID_USART0:
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA17, 1); /* TXD0 */
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA19, 0); /* RXD0 */
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/* CTS PA20 */
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/* RTS -- errata #39 PA21 */
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break;
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case AT91RM9200_ID_USART1:
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at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB20, 1); /* TXD1 */
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at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB21, 0); /* RXD1 */
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/* RI - PB18 */
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/* DTR - PB19 */
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/* DCD - PB23 */
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/* CTS - PB24 */
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/* DSR - PB25 */
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/* RTS - PB26 */
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break;
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case AT91RM9200_ID_USART2:
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA22, 0); /* RXD2 */
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA23, 1); /* TXD2 */
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/* CTS - PA30 B periph */
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/* RTS - PA31 B periph */
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break;
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case AT91RM9200_ID_USART3:
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at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA5, 1); /* TXD3 */
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at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA6, 0); /* RXD3 */
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/* CTS - PB0 B periph */
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/* RTS - PB1 B periph */
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break;
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default:
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break;
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}
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}
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void
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at91rm9200_config_mci(int has_4wire)
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{
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/* XXX TODO chip changed GPIO, other slots, etc */
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA27, 0); /* MCCK */
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA28, 1); /* MCCDA */
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA29, 1); /* MCDA0 */
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if (has_4wire) {
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at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB3, 1); /* MCDA1 */
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at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB4, 1); /* MCDA2 */
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at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB5, 1); /* MCDA3 */
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}
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}
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