freebsd-skq/sys/arm/xilinx
mmel a0d10caff7 EHCI: Make core reset and port speed reading more generic.
Use driver settable callbacks for handling of:
- core post reset
- reading actual port speed

Typically, OTG enabled EHCI cores wants setting of USBMODE register,
but this register is not defined in EHCI specification and different
cores can have it on different offset.

Also, for cores with TT extension, actual port speed must be determinable.
But again, EHCI specification not covers this so this patch provides
function for two most common variant of speed bits layout.

Reviewed by: hselasky
Differential Revision: https://reviews.freebsd.org/D5088
2016-01-28 14:11:59 +00:00
..
zedboard
files.zynq7
std.zynq7
uart_dev_cdnc.c
zy7_devcfg.c
zy7_ehci.c
zy7_gpio.c
zy7_l2cache.c
zy7_machdep.c
zy7_mp.c
zy7_reg.h
zy7_slcr.c
zy7_slcr.h