873043aeab
This fixes the issue of bhyve appearing to halt when using nmdm ports for the console, until a connection is made to the other end. bhyveload already does this. Reported by: Many. MFC after: 3 weeks.
624 lines
12 KiB
C
624 lines
12 KiB
C
/*-
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* Copyright (c) 2012 NetApp, Inc.
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <dev/ic/ns16550.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <fcntl.h>
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#include <termios.h>
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#include <unistd.h>
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#include <stdbool.h>
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#include <string.h>
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#include <pthread.h>
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#include "mevent.h"
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#include "uart_emul.h"
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#define COM1_BASE 0x3F8
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#define COM1_IRQ 4
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#define COM2_BASE 0x2F8
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#define COM2_IRQ 3
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#define DEFAULT_RCLK 1843200
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#define DEFAULT_BAUD 9600
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#define FCR_RX_MASK 0xC0
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#define MCR_OUT1 0x04
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#define MCR_OUT2 0x08
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#define MSR_DELTA_MASK 0x0f
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#ifndef REG_SCR
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#define REG_SCR com_scr
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#endif
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#define FIFOSZ 16
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static bool uart_stdio; /* stdio in use for i/o */
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static struct termios tio_stdio_orig;
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static struct {
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int baseaddr;
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int irq;
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bool inuse;
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} uart_lres[] = {
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{ COM1_BASE, COM1_IRQ, false},
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{ COM2_BASE, COM2_IRQ, false},
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};
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#define UART_NLDEVS (sizeof(uart_lres) / sizeof(uart_lres[0]))
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struct fifo {
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uint8_t buf[FIFOSZ];
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int rindex; /* index to read from */
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int windex; /* index to write to */
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int num; /* number of characters in the fifo */
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int size; /* size of the fifo */
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};
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struct ttyfd {
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bool opened;
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int fd; /* tty device file descriptor */
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struct termios tio_orig, tio_new; /* I/O Terminals */
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};
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struct uart_softc {
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pthread_mutex_t mtx; /* protects all softc elements */
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uint8_t data; /* Data register (R/W) */
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uint8_t ier; /* Interrupt enable register (R/W) */
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uint8_t lcr; /* Line control register (R/W) */
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uint8_t mcr; /* Modem control register (R/W) */
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uint8_t lsr; /* Line status register (R/W) */
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uint8_t msr; /* Modem status register (R/W) */
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uint8_t fcr; /* FIFO control register (W) */
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uint8_t scr; /* Scratch register (R/W) */
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uint8_t dll; /* Baudrate divisor latch LSB */
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uint8_t dlh; /* Baudrate divisor latch MSB */
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struct fifo rxfifo;
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struct ttyfd tty;
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bool thre_int_pending; /* THRE interrupt pending */
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void *arg;
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uart_intr_func_t intr_assert;
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uart_intr_func_t intr_deassert;
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};
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static void uart_drain(int fd, enum ev_type ev, void *arg);
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static void
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ttyclose(void)
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{
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tcsetattr(STDIN_FILENO, TCSANOW, &tio_stdio_orig);
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}
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static void
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ttyopen(struct ttyfd *tf)
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{
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tcgetattr(tf->fd, &tf->tio_orig);
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tf->tio_new = tf->tio_orig;
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cfmakeraw(&tf->tio_new);
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tf->tio_new.c_cflag |= CLOCAL;
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tcsetattr(tf->fd, TCSANOW, &tf->tio_new);
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if (tf->fd == STDIN_FILENO) {
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tio_stdio_orig = tf->tio_orig;
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atexit(ttyclose);
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}
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}
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static bool
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tty_char_available(struct ttyfd *tf)
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{
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fd_set rfds;
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struct timeval tv;
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FD_ZERO(&rfds);
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FD_SET(tf->fd, &rfds);
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tv.tv_sec = 0;
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tv.tv_usec = 0;
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if (select(tf->fd + 1, &rfds, NULL, NULL, &tv) > 0 ) {
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return (true);
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} else {
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return (false);
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}
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}
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static int
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ttyread(struct ttyfd *tf)
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{
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char rb;
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if (tty_char_available(tf)) {
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read(tf->fd, &rb, 1);
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return (rb & 0xff);
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} else {
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return (-1);
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}
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}
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static void
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ttywrite(struct ttyfd *tf, unsigned char wb)
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{
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(void)write(tf->fd, &wb, 1);
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}
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static void
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fifo_reset(struct fifo *fifo, int size)
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{
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bzero(fifo, sizeof(struct fifo));
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fifo->size = size;
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}
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static int
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fifo_putchar(struct fifo *fifo, uint8_t ch)
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{
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if (fifo->num < fifo->size) {
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fifo->buf[fifo->windex] = ch;
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fifo->windex = (fifo->windex + 1) % fifo->size;
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fifo->num++;
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return (0);
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} else
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return (-1);
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}
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static int
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fifo_getchar(struct fifo *fifo)
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{
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int c;
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if (fifo->num > 0) {
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c = fifo->buf[fifo->rindex];
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fifo->rindex = (fifo->rindex + 1) % fifo->size;
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fifo->num--;
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return (c);
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} else
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return (-1);
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}
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static int
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fifo_numchars(struct fifo *fifo)
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{
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return (fifo->num);
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}
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static int
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fifo_available(struct fifo *fifo)
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{
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return (fifo->num < fifo->size);
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}
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static void
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uart_opentty(struct uart_softc *sc)
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{
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struct mevent *mev;
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ttyopen(&sc->tty);
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mev = mevent_add(sc->tty.fd, EVF_READ, uart_drain, sc);
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assert(mev);
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}
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/*
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* The IIR returns a prioritized interrupt reason:
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* - receive data available
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* - transmit holding register empty
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* - modem status change
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*
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* Return an interrupt reason if one is available.
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*/
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static int
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uart_intr_reason(struct uart_softc *sc)
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{
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if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
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return (IIR_RLS);
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else if (fifo_numchars(&sc->rxfifo) > 0 && (sc->ier & IER_ERXRDY) != 0)
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return (IIR_RXTOUT);
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else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
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return (IIR_TXRDY);
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else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
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return (IIR_MLSC);
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else
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return (IIR_NOPEND);
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}
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static void
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uart_reset(struct uart_softc *sc)
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{
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uint16_t divisor;
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divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
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sc->dll = divisor;
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sc->dlh = divisor >> 16;
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fifo_reset(&sc->rxfifo, 1); /* no fifo until enabled by software */
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}
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/*
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* Toggle the COM port's intr pin depending on whether or not we have an
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* interrupt condition to report to the processor.
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*/
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static void
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uart_toggle_intr(struct uart_softc *sc)
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{
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uint8_t intr_reason;
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intr_reason = uart_intr_reason(sc);
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if (intr_reason == IIR_NOPEND)
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(*sc->intr_deassert)(sc->arg);
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else
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(*sc->intr_assert)(sc->arg);
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}
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static void
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uart_drain(int fd, enum ev_type ev, void *arg)
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{
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struct uart_softc *sc;
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int ch;
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sc = arg;
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assert(fd == sc->tty.fd);
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assert(ev == EVF_READ);
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/*
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* This routine is called in the context of the mevent thread
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* to take out the softc lock to protect against concurrent
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* access from a vCPU i/o exit
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*/
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pthread_mutex_lock(&sc->mtx);
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if ((sc->mcr & MCR_LOOPBACK) != 0) {
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(void) ttyread(&sc->tty);
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} else {
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while (fifo_available(&sc->rxfifo) &&
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((ch = ttyread(&sc->tty)) != -1)) {
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fifo_putchar(&sc->rxfifo, ch);
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}
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uart_toggle_intr(sc);
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}
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pthread_mutex_unlock(&sc->mtx);
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}
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void
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uart_write(struct uart_softc *sc, int offset, uint8_t value)
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{
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int fifosz;
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uint8_t msr;
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pthread_mutex_lock(&sc->mtx);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if ((sc->lcr & LCR_DLAB) != 0) {
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if (offset == REG_DLL) {
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sc->dll = value;
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goto done;
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}
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if (offset == REG_DLH) {
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sc->dlh = value;
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goto done;
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}
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}
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switch (offset) {
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case REG_DATA:
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if (sc->mcr & MCR_LOOPBACK) {
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if (fifo_putchar(&sc->rxfifo, value) != 0)
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sc->lsr |= LSR_OE;
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} else if (sc->tty.opened) {
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ttywrite(&sc->tty, value);
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} /* else drop on floor */
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sc->thre_int_pending = true;
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break;
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case REG_IER:
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/*
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* Apply mask so that bits 4-7 are 0
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* Also enables bits 0-3 only if they're 1
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*/
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sc->ier = value & 0x0F;
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break;
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case REG_FCR:
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/*
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* When moving from FIFO and 16450 mode and vice versa,
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* the FIFO contents are reset.
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*/
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if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
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fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
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fifo_reset(&sc->rxfifo, fifosz);
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}
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/*
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* The FCR_ENABLE bit must be '1' for the programming
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* of other FCR bits to be effective.
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*/
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if ((value & FCR_ENABLE) == 0) {
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sc->fcr = 0;
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} else {
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if ((value & FCR_RCV_RST) != 0)
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fifo_reset(&sc->rxfifo, FIFOSZ);
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sc->fcr = value &
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(FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
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}
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break;
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case REG_LCR:
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sc->lcr = value;
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break;
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case REG_MCR:
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/* Apply mask so that bits 5-7 are 0 */
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sc->mcr = value & 0x1F;
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msr = 0;
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if (sc->mcr & MCR_LOOPBACK) {
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/*
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* In the loopback mode certain bits from the
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* MCR are reflected back into MSR
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*/
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if (sc->mcr & MCR_RTS)
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msr |= MSR_CTS;
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if (sc->mcr & MCR_DTR)
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msr |= MSR_DSR;
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if (sc->mcr & MCR_OUT1)
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msr |= MSR_RI;
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if (sc->mcr & MCR_OUT2)
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msr |= MSR_DCD;
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}
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/*
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* Detect if there has been any change between the
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* previous and the new value of MSR. If there is
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* then assert the appropriate MSR delta bit.
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*/
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if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
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sc->msr |= MSR_DCTS;
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if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
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sc->msr |= MSR_DDSR;
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if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
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sc->msr |= MSR_DDCD;
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if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
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sc->msr |= MSR_TERI;
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/*
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* Update the value of MSR while retaining the delta
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* bits.
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*/
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sc->msr &= MSR_DELTA_MASK;
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sc->msr |= msr;
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break;
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case REG_LSR:
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/*
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* Line status register is not meant to be written to
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* during normal operation.
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*/
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break;
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case REG_MSR:
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/*
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* As far as I can tell MSR is a read-only register.
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*/
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break;
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case REG_SCR:
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sc->scr = value;
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break;
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default:
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break;
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}
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done:
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uart_toggle_intr(sc);
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pthread_mutex_unlock(&sc->mtx);
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}
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uint8_t
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uart_read(struct uart_softc *sc, int offset)
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{
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uint8_t iir, intr_reason, reg;
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pthread_mutex_lock(&sc->mtx);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if ((sc->lcr & LCR_DLAB) != 0) {
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if (offset == REG_DLL) {
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reg = sc->dll;
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goto done;
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}
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if (offset == REG_DLH) {
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reg = sc->dlh;
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goto done;
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}
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}
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switch (offset) {
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case REG_DATA:
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reg = fifo_getchar(&sc->rxfifo);
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break;
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case REG_IER:
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reg = sc->ier;
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break;
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case REG_IIR:
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iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
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intr_reason = uart_intr_reason(sc);
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/*
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* Deal with side effects of reading the IIR register
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*/
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if (intr_reason == IIR_TXRDY)
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sc->thre_int_pending = false;
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iir |= intr_reason;
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reg = iir;
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break;
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case REG_LCR:
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reg = sc->lcr;
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break;
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case REG_MCR:
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reg = sc->mcr;
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break;
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case REG_LSR:
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/* Transmitter is always ready for more data */
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sc->lsr |= LSR_TEMT | LSR_THRE;
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/* Check for new receive data */
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if (fifo_numchars(&sc->rxfifo) > 0)
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sc->lsr |= LSR_RXRDY;
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else
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sc->lsr &= ~LSR_RXRDY;
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reg = sc->lsr;
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/* The LSR_OE bit is cleared on LSR read */
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sc->lsr &= ~LSR_OE;
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break;
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case REG_MSR:
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/*
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* MSR delta bits are cleared on read
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*/
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reg = sc->msr;
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sc->msr &= ~MSR_DELTA_MASK;
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break;
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case REG_SCR:
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reg = sc->scr;
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break;
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default:
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reg = 0xFF;
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break;
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}
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done:
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uart_toggle_intr(sc);
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pthread_mutex_unlock(&sc->mtx);
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return (reg);
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}
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int
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uart_legacy_alloc(int which, int *baseaddr, int *irq)
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{
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if (which < 0 || which >= UART_NLDEVS || uart_lres[which].inuse)
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return (-1);
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uart_lres[which].inuse = true;
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*baseaddr = uart_lres[which].baseaddr;
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*irq = uart_lres[which].irq;
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return (0);
|
|
}
|
|
|
|
struct uart_softc *
|
|
uart_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
|
|
void *arg)
|
|
{
|
|
struct uart_softc *sc;
|
|
|
|
sc = malloc(sizeof(struct uart_softc));
|
|
bzero(sc, sizeof(struct uart_softc));
|
|
|
|
sc->arg = arg;
|
|
sc->intr_assert = intr_assert;
|
|
sc->intr_deassert = intr_deassert;
|
|
|
|
pthread_mutex_init(&sc->mtx, NULL);
|
|
|
|
uart_reset(sc);
|
|
|
|
return (sc);
|
|
}
|
|
|
|
static int
|
|
uart_tty_backend(struct uart_softc *sc, const char *opts)
|
|
{
|
|
int fd;
|
|
int retval;
|
|
|
|
retval = -1;
|
|
|
|
fd = open(opts, O_RDWR | O_NONBLOCK);
|
|
if (fd > 0 && isatty(fd)) {
|
|
sc->tty.fd = fd;
|
|
sc->tty.opened = true;
|
|
retval = 0;
|
|
}
|
|
|
|
return (retval);
|
|
}
|
|
|
|
int
|
|
uart_set_backend(struct uart_softc *sc, const char *opts)
|
|
{
|
|
int retval;
|
|
|
|
retval = -1;
|
|
|
|
if (opts == NULL)
|
|
return (0);
|
|
|
|
if (strcmp("stdio", opts) == 0) {
|
|
if (!uart_stdio) {
|
|
sc->tty.fd = STDIN_FILENO;
|
|
sc->tty.opened = true;
|
|
uart_stdio = true;
|
|
retval = 0;
|
|
}
|
|
} else if (uart_tty_backend(sc, opts) == 0) {
|
|
retval = 0;
|
|
}
|
|
|
|
if (retval == 0)
|
|
uart_opentty(sc);
|
|
|
|
return (retval);
|
|
}
|