511 lines
12 KiB
C
511 lines
12 KiB
C
/*-
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* Copyright (c) 2007 Yahoo!, Inc.
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* All rights reserved.
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* Written by: John Baldwin <jhb@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef lint
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static const char rcsid[] =
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"$FreeBSD$";
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#endif /* not lint */
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#include <sys/types.h>
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#include <err.h>
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#include <stdio.h>
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#include <sys/agpio.h>
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#include <sys/pciio.h>
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#include <dev/agp/agpreg.h>
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#include <dev/pci/pcireg.h>
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#include "pciconf.h"
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static void
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cap_power(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint16_t cap, status;
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cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
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status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
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printf("powerspec %d supports D0%s%s D3 current D%d",
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cap & PCIM_PCAP_SPEC,
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cap & PCIM_PCAP_D1SUPP ? " D1" : "",
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cap & PCIM_PCAP_D2SUPP ? " D2" : "",
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status & PCIM_PSTAT_DMASK);
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}
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static void
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cap_agp(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint32_t status, command;
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status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
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command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
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printf("AGP ");
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if (AGP_MODE_GET_MODE_3(status)) {
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printf("v3 ");
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if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x)
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printf("8x ");
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if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x)
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printf("4x ");
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} else {
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if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x)
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printf("4x ");
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if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x)
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printf("2x ");
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if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x)
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printf("1x ");
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}
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if (AGP_MODE_GET_SBA(status))
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printf("SBA ");
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if (AGP_MODE_GET_AGP(command)) {
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printf("enabled at ");
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if (AGP_MODE_GET_MODE_3(command)) {
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printf("v3 ");
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switch (AGP_MODE_GET_RATE(command)) {
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case AGP_MODE_V3_RATE_8x:
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printf("8x ");
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break;
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case AGP_MODE_V3_RATE_4x:
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printf("4x ");
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break;
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}
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} else
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switch (AGP_MODE_GET_RATE(command)) {
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case AGP_MODE_V2_RATE_4x:
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printf("4x ");
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break;
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case AGP_MODE_V2_RATE_2x:
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printf("2x ");
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break;
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case AGP_MODE_V2_RATE_1x:
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printf("1x ");
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break;
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}
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if (AGP_MODE_GET_SBA(command))
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printf("SBA ");
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} else
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printf("disabled");
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}
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static void
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cap_vpd(int fd, struct pci_conf *p, uint8_t ptr)
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{
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printf("VPD");
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}
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static void
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cap_msi(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint16_t ctrl;
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int msgnum;
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ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
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msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
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printf("MSI supports %d message%s%s%s ", msgnum,
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(msgnum == 1) ? "" : "s",
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(ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
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(ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : "");
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if (ctrl & PCIM_MSICTRL_MSI_ENABLE) {
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msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4);
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printf("enabled with %d message%s", msgnum,
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(msgnum == 1) ? "" : "s");
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}
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}
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static void
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cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint32_t status;
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int comma, max_splits, max_burst_read;
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status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
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printf("PCI-X ");
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if (status & PCIXM_STATUS_64BIT)
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printf("64-bit ");
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if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
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printf("bridge ");
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printf("supports");
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comma = 0;
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if (status & PCIXM_STATUS_133CAP) {
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printf("%s 133MHz", comma ? "," : "");
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comma = 1;
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}
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if (status & PCIXM_STATUS_266CAP) {
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printf("%s 266MHz", comma ? "," : "");
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comma = 1;
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}
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if (status & PCIXM_STATUS_533CAP) {
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printf("%s 533MHz", comma ? "," : "");
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comma = 1;
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}
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if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
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return;
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switch (status & PCIXM_STATUS_MAX_READ) {
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case PCIXM_STATUS_MAX_READ_512:
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max_burst_read = 512;
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break;
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case PCIXM_STATUS_MAX_READ_1024:
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max_burst_read = 1024;
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break;
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case PCIXM_STATUS_MAX_READ_2048:
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max_burst_read = 2048;
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break;
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case PCIXM_STATUS_MAX_READ_4096:
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max_burst_read = 4096;
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break;
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}
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switch (status & PCIXM_STATUS_MAX_SPLITS) {
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case PCIXM_STATUS_MAX_SPLITS_1:
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max_splits = 1;
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break;
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case PCIXM_STATUS_MAX_SPLITS_2:
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max_splits = 2;
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break;
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case PCIXM_STATUS_MAX_SPLITS_3:
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max_splits = 3;
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break;
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case PCIXM_STATUS_MAX_SPLITS_4:
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max_splits = 4;
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break;
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case PCIXM_STATUS_MAX_SPLITS_8:
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max_splits = 8;
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break;
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case PCIXM_STATUS_MAX_SPLITS_12:
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max_splits = 12;
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break;
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case PCIXM_STATUS_MAX_SPLITS_16:
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max_splits = 16;
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break;
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case PCIXM_STATUS_MAX_SPLITS_32:
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max_splits = 32;
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break;
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}
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printf("%s %d burst read, %d split transaction%s", comma ? "," : "",
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max_burst_read, max_splits, max_splits == 1 ? "" : "s");
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}
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static void
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cap_ht(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint32_t reg;
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uint16_t command;
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command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
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printf("HT ");
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if ((command & 0xe000) == PCIM_HTCAP_SLAVE)
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printf("slave");
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else if ((command & 0xe000) == PCIM_HTCAP_HOST)
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printf("host");
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else
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switch (command & PCIM_HTCMD_CAP_MASK) {
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case PCIM_HTCAP_SWITCH:
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printf("switch");
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break;
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case PCIM_HTCAP_INTERRUPT:
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printf("interrupt");
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break;
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case PCIM_HTCAP_REVISION_ID:
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printf("revision ID");
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break;
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case PCIM_HTCAP_UNITID_CLUMPING:
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printf("unit ID clumping");
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break;
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case PCIM_HTCAP_EXT_CONFIG_SPACE:
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printf("extended config space");
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break;
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case PCIM_HTCAP_ADDRESS_MAPPING:
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printf("address mapping");
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break;
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case PCIM_HTCAP_MSI_MAPPING:
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printf("MSI %saddress window %s at 0x",
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command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "",
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command & PCIM_HTCMD_MSI_ENABLE ? "enabled" :
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"disabled");
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if (command & PCIM_HTCMD_MSI_FIXED)
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printf("fee00000");
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else {
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reg = read_config(fd, &p->pc_sel,
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ptr + PCIR_HTMSI_ADDRESS_HI, 4);
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if (reg != 0)
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printf("%08x", reg);
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reg = read_config(fd, &p->pc_sel,
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ptr + PCIR_HTMSI_ADDRESS_LO, 4);
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printf("%08x", reg);
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}
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break;
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case PCIM_HTCAP_DIRECT_ROUTE:
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printf("direct route");
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break;
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case PCIM_HTCAP_VCSET:
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printf("VC set");
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break;
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case PCIM_HTCAP_RETRY_MODE:
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printf("retry mode");
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break;
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case PCIM_HTCAP_X86_ENCODING:
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printf("X86 encoding");
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break;
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default:
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printf("unknown %02x", command);
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break;
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}
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}
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static void
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cap_vendor(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint8_t length;
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length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
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printf("vendor (length %d)", length);
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if (p->pc_vendor == 0x8086) {
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/* Intel */
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uint8_t version;
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version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
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1);
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printf(" Intel cap %d version %d", version >> 4, version & 0xf);
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if (version >> 4 == 1 && length == 12) {
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/* Feature Detection */
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uint32_t fvec;
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int comma;
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comma = 0;
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fvec = read_config(fd, &p->pc_sel, ptr +
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PCIR_VENDOR_DATA + 5, 4);
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printf("\n\t\t features:");
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if (fvec & (1 << 0)) {
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printf(" AMT");
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comma = 1;
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}
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fvec = read_config(fd, &p->pc_sel, ptr +
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PCIR_VENDOR_DATA + 1, 4);
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if (fvec & (1 << 21)) {
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printf("%s Quick Resume", comma ? "," : "");
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comma = 1;
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}
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if (fvec & (1 << 18)) {
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printf("%s SATA RAID-5", comma ? "," : "");
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comma = 1;
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}
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if (fvec & (1 << 9)) {
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printf("%s Mobile", comma ? "," : "");
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comma = 1;
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}
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if (fvec & (1 << 7)) {
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printf("%s 6 PCI-e x1 slots", comma ? "," : "");
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comma = 1;
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} else {
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printf("%s 4 PCI-e x1 slots", comma ? "," : "");
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comma = 1;
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}
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if (fvec & (1 << 5)) {
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printf("%s SATA RAID-0/1/10", comma ? "," : "");
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comma = 1;
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}
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if (fvec & (1 << 3)) {
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printf("%s SATA AHCI", comma ? "," : "");
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comma = 1;
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}
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}
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}
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}
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static void
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cap_debug(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint16_t debug_port;
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debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
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printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port &
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PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13));
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}
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static void
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cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint32_t id;
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id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
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printf("PCI Bridge card=0x%08x", id);
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}
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static void
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cap_express(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint16_t flags;
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flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2);
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printf("PCI-Express %d ", flags & PCIM_EXP_FLAGS_VERSION);
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switch (flags & PCIM_EXP_FLAGS_TYPE) {
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case PCIM_EXP_TYPE_ENDPOINT:
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printf("endpoint");
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break;
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case PCIM_EXP_TYPE_LEGACY_ENDPOINT:
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printf("legacy endpoint");
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break;
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case PCIM_EXP_TYPE_ROOT_PORT:
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printf("root port");
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break;
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case PCIM_EXP_TYPE_UPSTREAM_PORT:
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printf("upstream port");
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break;
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case PCIM_EXP_TYPE_DOWNSTREAM_PORT:
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printf("downstream port");
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break;
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case PCIM_EXP_TYPE_PCI_BRIDGE:
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printf("PCI bridge");
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break;
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default:
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printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 8);
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break;
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}
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if (flags & PCIM_EXP_FLAGS_IRQ)
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printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 17);
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}
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static void
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cap_msix(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint32_t val;
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uint16_t ctrl;
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int msgnum, table_bar, pba_bar;
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ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
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msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
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val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
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table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
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val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
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pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
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printf("MSI-X supports %d message%s ", msgnum,
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(msgnum == 1) ? "" : "s");
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if (table_bar == pba_bar)
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printf("in map 0x%x", table_bar);
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else
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printf("in maps 0x%x and 0x%x", table_bar, pba_bar);
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if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE)
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printf(" enabled");
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}
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static void
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cap_sata(int fd, struct pci_conf *p, uint8_t ptr)
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{
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printf("SATA Index-Data Pair");
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}
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static void
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cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint8_t cap;
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cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
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printf("PCI Advanced Features:%s%s",
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cap & PCIM_PCIAFCAP_FLR ? " FLR" : "",
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cap & PCIM_PCIAFCAP_TP ? " TP" : "");
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}
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void
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list_caps(int fd, struct pci_conf *p)
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{
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uint16_t cmd;
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uint8_t ptr, cap;
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/* Are capabilities present for this device? */
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cmd = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
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if (!(cmd & PCIM_STATUS_CAPPRESENT))
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return;
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switch (p->pc_hdr & PCIM_HDRTYPE) {
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case 0:
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case 1:
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ptr = PCIR_CAP_PTR;
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break;
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case 2:
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ptr = PCIR_CAP_PTR_2;
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break;
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default:
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errx(1, "list_caps: bad header type");
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}
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/* Walk the capability list. */
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ptr = read_config(fd, &p->pc_sel, ptr, 1);
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while (ptr != 0 && ptr != 0xff) {
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cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
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printf(" cap %02x[%02x] = ", cap, ptr);
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switch (cap) {
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case PCIY_PMG:
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cap_power(fd, p, ptr);
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break;
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case PCIY_AGP:
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cap_agp(fd, p, ptr);
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break;
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case PCIY_VPD:
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cap_vpd(fd, p, ptr);
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break;
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case PCIY_MSI:
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cap_msi(fd, p, ptr);
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break;
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case PCIY_PCIX:
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cap_pcix(fd, p, ptr);
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break;
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case PCIY_HT:
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cap_ht(fd, p, ptr);
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break;
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case PCIY_VENDOR:
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cap_vendor(fd, p, ptr);
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break;
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case PCIY_DEBUG:
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cap_debug(fd, p, ptr);
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break;
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case PCIY_SUBVENDOR:
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cap_subvendor(fd, p, ptr);
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break;
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case PCIY_EXPRESS:
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cap_express(fd, p, ptr);
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break;
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case PCIY_MSIX:
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cap_msix(fd, p, ptr);
|
|
break;
|
|
case PCIY_SATA:
|
|
cap_sata(fd, p, ptr);
|
|
break;
|
|
case PCIY_PCIAF:
|
|
cap_pciaf(fd, p, ptr);
|
|
break;
|
|
default:
|
|
printf("unknown");
|
|
break;
|
|
}
|
|
printf("\n");
|
|
ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
|
|
}
|
|
}
|