56ae1bed48
variations (e500 currently), this provides a gcc-level FPU emulation and is an alternative approach to the recently introduced kernel-level emulation (FPU_EMU). Approved by: cognet (mentor) MFp4: e500
269 lines
6.4 KiB
C
269 lines
6.4 KiB
C
/*-
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* Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _FENV_H_
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#define _FENV_H_
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#include <sys/_types.h>
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typedef __uint32_t fenv_t;
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typedef __uint32_t fexcept_t;
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/* Exception flags */
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#define FE_INEXACT 0x02000000
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#define FE_DIVBYZERO 0x04000000
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#define FE_UNDERFLOW 0x08000000
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#define FE_OVERFLOW 0x10000000
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#define FE_INVALID 0x20000000 /* all types of invalid FP ops */
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/*
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* The PowerPC architecture has extra invalid flags that indicate the
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* specific type of invalid operation occurred. These flags may be
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* tested, set, and cleared---but not masked---separately. All of
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* these bits are cleared when FE_INVALID is cleared, but only
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* FE_VXSOFT is set when FE_INVALID is explicitly set in software.
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*/
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#define FE_VXCVI 0x00000100 /* invalid integer convert */
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#define FE_VXSQRT 0x00000200 /* square root of a negative */
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#define FE_VXSOFT 0x00000400 /* software-requested exception */
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#define FE_VXVC 0x00080000 /* ordered comparison involving NaN */
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#define FE_VXIMZ 0x00100000 /* inf * 0 */
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#define FE_VXZDZ 0x00200000 /* 0 / 0 */
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#define FE_VXIDI 0x00400000 /* inf / inf */
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#define FE_VXISI 0x00800000 /* inf - inf */
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#define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */
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#define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
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FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
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FE_VXSNAN | FE_INVALID)
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#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
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FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
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/* Rounding modes */
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#define FE_TONEAREST 0x0000
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#define FE_TOWARDZERO 0x0001
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#define FE_UPWARD 0x0002
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#define FE_DOWNWARD 0x0003
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#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
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FE_UPWARD | FE_TOWARDZERO)
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__BEGIN_DECLS
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/* Default floating-point environment */
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extern const fenv_t __fe_dfl_env;
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#define FE_DFL_ENV (&__fe_dfl_env)
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/* We need to be able to map status flag positions to mask flag positions */
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#define _FPUSW_SHIFT 22
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#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
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FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
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#ifndef _SOFT_FLOAT
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#define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env)))
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#define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env))
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#else
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#define __mffs(__env)
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#define __mtfsf(__env)
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#endif
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union __fpscr {
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double __d;
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struct {
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__uint32_t __junk;
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fenv_t __reg;
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} __bits;
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};
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static __inline int
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feclearexcept(int __excepts)
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{
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union __fpscr __r;
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if (__excepts & FE_INVALID)
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__excepts |= FE_ALL_INVALID;
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__mffs(&__r.__d);
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__r.__bits.__reg &= ~__excepts;
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__mtfsf(__r.__d);
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return (0);
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}
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static __inline int
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fegetexceptflag(fexcept_t *__flagp, int __excepts)
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{
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union __fpscr __r;
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__mffs(&__r.__d);
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*__flagp = __r.__bits.__reg & __excepts;
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return (0);
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}
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static __inline int
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fesetexceptflag(const fexcept_t *__flagp, int __excepts)
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{
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union __fpscr __r;
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if (__excepts & FE_INVALID)
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__excepts |= FE_ALL_EXCEPT;
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__mffs(&__r.__d);
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__r.__bits.__reg &= ~__excepts;
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__r.__bits.__reg |= *__flagp & __excepts;
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__mtfsf(__r.__d);
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return (0);
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}
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static __inline int
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feraiseexcept(int __excepts)
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{
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union __fpscr __r;
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if (__excepts & FE_INVALID)
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__excepts |= FE_VXSOFT;
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__mffs(&__r.__d);
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__r.__bits.__reg |= __excepts;
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__mtfsf(__r.__d);
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return (0);
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}
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static __inline int
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fetestexcept(int __excepts)
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{
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union __fpscr __r;
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__mffs(&__r.__d);
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return (__r.__bits.__reg & __excepts);
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}
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static __inline int
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fegetround(void)
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{
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union __fpscr __r;
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__mffs(&__r.__d);
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return (__r.__bits.__reg & _ROUND_MASK);
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}
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static __inline int
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fesetround(int __round)
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{
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union __fpscr __r;
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if (__round & ~_ROUND_MASK)
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return (-1);
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__mffs(&__r.__d);
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__r.__bits.__reg &= ~_ROUND_MASK;
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__r.__bits.__reg |= __round;
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__mtfsf(__r.__d);
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return (0);
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}
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static __inline int
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fegetenv(fenv_t *__envp)
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{
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union __fpscr __r;
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__mffs(&__r.__d);
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*__envp = __r.__bits.__reg;
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return (0);
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}
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static __inline int
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feholdexcept(fenv_t *__envp)
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{
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union __fpscr __r;
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__mffs(&__r.__d);
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*__envp = __r.__d;
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__r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
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__mtfsf(__r.__d);
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return (0);
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}
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static __inline int
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fesetenv(const fenv_t *__envp)
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{
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union __fpscr __r;
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__r.__bits.__reg = *__envp;
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__mtfsf(__r.__d);
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return (0);
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}
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static __inline int
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feupdateenv(const fenv_t *__envp)
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{
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union __fpscr __r;
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__mffs(&__r.__d);
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__r.__bits.__reg &= FE_ALL_EXCEPT;
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__r.__bits.__reg |= *__envp;
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__mtfsf(__r.__d);
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return (0);
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}
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#if __BSD_VISIBLE
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static __inline int
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feenableexcept(int __mask)
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{
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union __fpscr __r;
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fenv_t __oldmask;
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__mffs(&__r.__d);
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__oldmask = __r.__bits.__reg;
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__r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
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__mtfsf(__r.__d);
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return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
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}
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static __inline int
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fedisableexcept(int __mask)
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{
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union __fpscr __r;
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fenv_t __oldmask;
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__mffs(&__r.__d);
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__oldmask = __r.__bits.__reg;
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__r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
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__mtfsf(__r.__d);
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return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
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}
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static __inline int
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fegetexcept(void)
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{
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union __fpscr __r;
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__mffs(&__r.__d);
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return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
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}
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#endif /* __BSD_VISIBLE */
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__END_DECLS
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#endif /* !_FENV_H_ */
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