5ee00411e4
DMA handles all data transfers up to 128K or 16 segments and fallback to pio mode when DMA requirements are not met. The read performance has improved greatly while the write performance also showed some improvement but seems limited by the card type and quality. Submitted by: Pratik Singhal <pratiksinghal@freebsd.org> Sponsored by: Google Summer of Code 2015 Tested on: A10 (cubieboard) and A20 (cubieboard 2 and banana pi)
199 lines
7.7 KiB
C
199 lines
7.7 KiB
C
/*-
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* Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _A10_MMC_H_
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#define _A10_MMC_H_
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#define A10_MMC_GCTRL 0x00 /* Global Control Register */
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#define A10_MMC_CLKCR 0x04 /* Clock Control Register */
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#define A10_MMC_TIMEOUT 0x08 /* Timeout Register */
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#define A10_MMC_WIDTH 0x0C /* Bus Width Register */
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#define A10_MMC_BLKSZ 0x10 /* Block Size Register */
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#define A10_MMC_BCNTR 0x14 /* Byte Count Register */
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#define A10_MMC_CMDR 0x18 /* Command Register */
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#define A10_MMC_CARG 0x1C /* Argument Register */
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#define A10_MMC_RESP0 0x20 /* Response Register 0 */
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#define A10_MMC_RESP1 0x24 /* Response Register 1 */
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#define A10_MMC_RESP2 0x28 /* Response Register 2 */
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#define A10_MMC_RESP3 0x2C /* Response Register 3 */
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#define A10_MMC_IMASK 0x30 /* Interrupt Mask Register */
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#define A10_MMC_MISTA 0x34 /* Masked Interrupt Status Register */
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#define A10_MMC_RINTR 0x38 /* Raw Interrupt Status Register */
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#define A10_MMC_STAS 0x3C /* Status Register */
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#define A10_MMC_FTRGL 0x40 /* FIFO Threshold Watermark Register */
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#define A10_MMC_FUNS 0x44 /* Function Select Register */
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#define A10_MMC_CBCR 0x48 /* CIU Byte Count Register */
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#define A10_MMC_BBCR 0x4C /* BIU Byte Count Register */
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#define A10_MMC_DBGC 0x50 /* Debug Enable Register */
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#define A10_MMC_DMAC 0x80 /* IDMAC Control Register */
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#define A10_MMC_DLBA 0x84 /* IDMAC Desc List Base Address Reg */
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#define A10_MMC_IDST 0x88 /* IDMAC Status Register */
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#define A10_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */
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#define A10_MMC_CHDA 0x90
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#define A10_MMC_CBDA 0x94
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#define A10_MMC_FIFO 0x100 /* FIFO Access Address */
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/* A10_MMC_GCTRL */
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#define A10_MMC_SOFT_RESET (1U << 0)
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#define A10_MMC_FIFO_RESET (1U << 1)
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#define A10_MMC_DMA_RESET (1U << 2)
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#define A10_MMC_INT_ENABLE (1U << 4)
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#define A10_MMC_DMA_ENABLE (1U << 5)
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#define A10_MMC_DEBOUNCE_ENABLE (1U << 8)
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#define A10_MMC_DDR_MODE (1U << 10)
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#define A10_MMC_ACCESS_BY_AHB (1U << 31)
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#define A10_MMC_RESET \
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(A10_MMC_SOFT_RESET | A10_MMC_FIFO_RESET | A10_MMC_DMA_RESET)
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/* A10_MMC_CLKCR */
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#define A10_MMC_CARD_CLK_ON (1U << 16)
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#define A10_MMC_LOW_POWER_ON (1U << 17)
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#define A10_MMC_CLKCR_DIV 0xff
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/* A10_MMC_WIDTH */
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#define A10_MMC_WIDTH1 0
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#define A10_MMC_WIDTH4 1
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#define A10_MMC_WIDTH8 2
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/* A10_MMC_CMDR */
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#define A10_MMC_RESP_EXP (1U << 6)
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#define A10_MMC_LONG_RESP (1U << 7)
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#define A10_MMC_CHECK_RESP_CRC (1U << 8)
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#define A10_MMC_DATA_EXP (1U << 9)
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#define A10_MMC_WRITE (1U << 10)
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#define A10_MMC_SEQ_MODE (1U << 11)
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#define A10_MMC_SEND_AUTOSTOP (1U << 12)
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#define A10_MMC_WAIT_PREOVER (1U << 13)
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#define A10_MMC_STOP_ABORT_CMD (1U << 14)
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#define A10_MMC_SEND_INIT_SEQ (1U << 15)
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#define A10_MMC_UPCLK_ONLY (1U << 21)
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#define A10_MMC_RDCEATADEV (1U << 22)
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#define A10_MMC_CCS_EXP (1U << 23)
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#define A10_MMC_ENB_BOOT (1U << 24)
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#define A10_MMC_ALT_BOOT_OPT (1U << 25)
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#define A10_MMC_BOOT_ACK_EXP (1U << 26)
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#define A10_MMC_DISABLE_BOOT (1U << 27)
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#define A10_MMC_VOL_SWITCH (1U << 28)
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#define A10_MMC_START (1U << 31)
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/* A10_MMC_IMASK and A10_MMC_RINTR */
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#define A10_MMC_RESP_ERR (1U << 1)
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#define A10_MMC_CMD_DONE (1U << 2)
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#define A10_MMC_DATA_OVER (1U << 3)
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#define A10_MMC_TX_DATA_REQ (1U << 4)
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#define A10_MMC_RX_DATA_REQ (1U << 5)
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#define A10_MMC_RESP_CRC_ERR (1U << 6)
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#define A10_MMC_DATA_CRC_ERR (1U << 7)
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#define A10_MMC_RESP_TIMEOUT (1U << 8)
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#define A10_MMC_ACK_RECV (1U << 8)
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#define A10_MMC_DATA_TIMEOUT (1U << 9)
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#define A10_MMC_BOOT_START (1U << 9)
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#define A10_MMC_DATA_STARVE (1U << 10)
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#define A10_MMC_VOL_CHG_DONE (1U << 10)
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#define A10_MMC_FIFO_RUN_ERR (1U << 11)
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#define A10_MMC_HARDW_LOCKED (1U << 12)
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#define A10_MMC_START_BIT_ERR (1U << 13)
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#define A10_MMC_AUTOCMD_DONE (1U << 14)
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#define A10_MMC_END_BIT_ERR (1U << 15)
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#define A10_MMC_SDIO_INT (1U << 16)
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#define A10_MMC_CARD_INSERT (1U << 30)
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#define A10_MMC_CARD_REMOVE (1U << 31)
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#define A10_MMC_INT_ERR_BIT \
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(A10_MMC_RESP_ERR | A10_MMC_RESP_CRC_ERR | \
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A10_MMC_DATA_CRC_ERR | A10_MMC_RESP_TIMEOUT | \
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A10_MMC_FIFO_RUN_ERR | A10_MMC_HARDW_LOCKED | \
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A10_MMC_START_BIT_ERR | A10_MMC_END_BIT_ERR)
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/* A10_MMC_STAS */
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#define A10_MMC_RX_WLFLAG (1U << 0)
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#define A10_MMC_TX_WLFLAG (1U << 1)
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#define A10_MMC_FIFO_EMPTY (1U << 2)
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#define A10_MMC_FIFO_FULL (1U << 3)
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#define A10_MMC_CARD_PRESENT (1U << 8)
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#define A10_MMC_CARD_DATA_BUSY (1U << 9)
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#define A10_MMC_DATA_FSM_BUSY (1U << 10)
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#define A10_MMC_DMA_REQ (1U << 31)
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#define A10_MMC_FIFO_SIZE 16
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/* A10_MMC_FUNS */
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#define A10_MMC_CE_ATA_ON (0xceaaU << 16)
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#define A10_MMC_SEND_IRQ_RESP (1U << 0)
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#define A10_MMC_SDIO_RD_WAIT (1U << 1)
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#define A10_MMC_ABT_RD_DATA (1U << 2)
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#define A10_MMC_SEND_CC_SD (1U << 8)
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#define A10_MMC_SEND_AUTOSTOP_CC_SD (1U << 9)
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#define A10_MMC_CE_ATA_DEV_INT_ENB (1U << 10)
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/* IDMA CONTROLLER BUS MOD BIT FIELD */
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#define A10_MMC_IDMAC_SOFT_RST (1U << 0)
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#define A10_MMC_IDMAC_FIX_BURST (1U << 1)
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#define A10_MMC_IDMAC_IDMA_ON (1U << 7)
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#define A10_MMC_IDMAC_REFETCH_DES (1U << 31)
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/* A10_MMC_IDST */
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#define A10_MMC_IDMAC_TRANSMIT_INT (1U << 0)
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#define A10_MMC_IDMAC_RECEIVE_INT (1U << 1)
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#define A10_MMC_IDMAC_FATAL_BUS_ERR (1U << 2)
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#define A10_MMC_IDMAC_DES_INVALID (1U << 4)
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#define A10_MMC_IDMAC_CARD_ERR_SUM (1U << 5)
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#define A10_MMC_IDMAC_NORMAL_INT_SUM (1U << 8)
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#define A10_MMC_IDMAC_ABNORMAL_INT_SUM (1U << 9)
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#define A10_MMC_IDMAC_HOST_ABT_INTX (1U << 10)
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#define A10_MMC_IDMAC_HOST_ABT_INRX (1U << 10)
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#define A10_MMC_IDMAC_IDLE (0U << 13)
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#define A10_MMC_IDMAC_SUSPEND (1U << 13)
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#define A10_MMC_IDMAC_DESC_RD (2U << 13)
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#define A10_MMC_IDMAC_DESC_CHECK (3U << 13)
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#define A10_MMC_IDMAC_RD_REQ_WAIT (4U << 13)
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#define A10_MMC_IDMAC_WR_REQ_WAIT (5U << 13)
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#define A10_MMC_IDMAC_RD (6U << 13)
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#define A10_MMC_IDMAC_WR (7U << 13)
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#define A10_MMC_IDMAC_DESC_CLOSE (8U << 13)
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#define A10_MMC_IDMAC_ERROR \
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(A10_MMC_IDMAC_FATAL_BUS_ERR | A10_MMC_IDMAC_CARD_ERR_SUM | \
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A10_MMC_IDMAC_DES_INVALID | A10_MMC_IDMAC_ABNORMAL_INT_SUM)
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#define A10_MMC_IDMAC_COMPLETE \
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(A10_MMC_IDMAC_TRANSMIT_INT | A10_MMC_IDMAC_RECEIVE_INT)
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/* The DMA descriptor table. */
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struct a10_mmc_dma_desc {
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uint32_t config;
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#define A10_MMC_DMA_CONFIG_DIC (1U << 1)
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#define A10_MMC_DMA_CONFIG_LD (1U << 2)
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#define A10_MMC_DMA_CONFIG_FD (1U << 3)
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#define A10_MMC_DMA_CONFIG_CH (1U << 4)
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#define A10_MMC_DMA_CONFIG_ER (1U << 5)
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#define A10_MMC_DMA_CONFIG_CES (1U << 30)
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#define A10_MMC_DMA_CONFIG_OWN (1U << 31)
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uint32_t buf_size;
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uint32_t buf_addr;
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uint32_t next;
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};
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#endif /* _A10_MMC_H_ */
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