88afb90f3c
This is the vastly updated cx drvier from Roman Kurakin <rik@cronyx.ru> who has been patiently waiting for this update for sometime. The driver is mostly a rewrite from the version we have in the tree. While some similarities remain, losing the little history that the old driver has is not a big loss, and the re@ felt it was easier this way (less error prone). The userland parts of this update will be committed shortly. The driver is not connected to the build yet. I want to make sure I don't break any platform at any time, so I want to test that with these files in the tree before I continue (on the off chance I'm forgetting a file). I changed the DEBUG macro to CX_DEBUG from the code that was submitted (to not break when we go to building with opt_global.h after the release), as well adding $FreeBSD$. Submitted by: Roman Kurakin Approved by: re@ <scottl>
488 lines
18 KiB
C
488 lines
18 KiB
C
/*
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* Defines for Cronyx-Sigma adapter driver.
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*
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* Copyright (C) 1994-2001 Cronyx Engineering.
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* Author: Serge Vakulenko, <vak@cronyx.ru>
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*
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* Copyright (C) 1998-2003 Cronyx Engineering.
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* Author: Roman Kurakin, <rik@cronyx.ru>
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*
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* This software is distributed with NO WARRANTIES, not even the implied
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* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Authors grant any other persons or organisations permission to use
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* or modify this software as long as this message is kept with the software,
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* all derivative works or modified versions.
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*
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* Cronyx Id: cxddk.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $
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* $FreeBSD$
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*/
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#ifndef port_t
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# ifdef _M_ALPHA /* port address on Alpha under */
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# define port_t unsigned long /* Windows NT is 32 bit long */
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# else
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# define port_t unsigned short /* all other architectures */
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# endif /* have 16-bit port addresses */
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#endif
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#define NBRD 3 /* the max number of installed boards */
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#define NPORT 32 /* the number of i/o ports per board */
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#define DMABUFSZ 1600
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/*
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* Asynchronous channel mode -------------------------------------------------
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*/
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/* Parity */
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#define PAR_EVEN 0 /* even parity */
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#define PAR_ODD 1 /* odd parity */
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/* Parity mode */
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#define PARM_NOPAR 0 /* no parity */
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#define PARM_FORCE 1 /* force parity (odd = force 1, even = 0) */
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#define PARM_NORMAL 2 /* normal parity */
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/* Flow control transparency mode */
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#define FLOWCC_PASS 0 /* pass flow ctl chars as exceptions */
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#define FLOWCC_NOTPASS 1 /* don't pass flow ctl chars to the host */
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/* Stop bit length */
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#define STOPB_1 2 /* 1 stop bit */
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#define STOPB_15 3 /* 1.5 stop bits */
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#define STOPB_2 4 /* 2 stop bits */
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/* Action on break condition */
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#define BRK_INTR 0 /* generate an exception interrupt */
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#define BRK_NULL 1 /* translate to a NULL character */
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#define BRK_RESERVED 2 /* reserved */
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#define BRK_DISCARD 3 /* discard character */
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/* Parity/framing error actions */
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#define PERR_INTR 0 /* generate an exception interrupt */
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#define PERR_NULL 1 /* translate to a NULL character */
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#define PERR_IGNORE 2 /* ignore error; char passed as good data */
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#define PERR_DISCARD 3 /* discard error character */
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#define PERR_FFNULL 5 /* translate to FF NULL char */
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typedef struct { /* async channel option register 1 */
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unsigned charlen : 4; /* character length, 5..8 */
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unsigned ignpar : 1; /* ignore parity */
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unsigned parmode : 2; /* parity mode */
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unsigned parity : 1; /* parity */
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} cx_cor1_async_t;
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typedef struct { /* async channel option register 2 */
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unsigned dsrae : 1; /* DSR automatic enable */
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unsigned ctsae : 1; /* CTS automatic enable */
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unsigned rtsao : 1; /* RTS automatic output enable */
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unsigned rlm : 1; /* remote loopback mode enable */
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unsigned zero : 1;
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unsigned etc : 1; /* embedded transmitter cmd enable */
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unsigned ixon : 1; /* in-band XON/XOFF enable */
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unsigned ixany : 1; /* XON on any character */
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} cx_cor2_async_t;
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typedef struct { /* async channel option register 3 */
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unsigned stopb : 3; /* stop bit length */
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unsigned zero : 1;
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unsigned scde : 1; /* special char detection enable */
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unsigned flowct : 1; /* flow control transparency mode */
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unsigned rngde : 1; /* range detect enable */
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unsigned escde : 1; /* extended spec. char detect enable */
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} cx_cor3_async_t;
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typedef struct { /* async channel option register 6 */
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unsigned parerr : 3; /* parity/framing error actions */
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unsigned brk : 2; /* action on break condition */
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unsigned inlcr : 1; /* translate NL to CR on input */
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unsigned icrnl : 1; /* translate CR to NL on input */
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unsigned igncr : 1; /* discard CR on input */
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} cx_cor6_async_t;
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typedef struct { /* async channel option register 7 */
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unsigned ocrnl : 1; /* translate CR to NL on output */
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unsigned onlcr : 1; /* translate NL to CR on output */
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unsigned zero : 3;
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unsigned fcerr : 1; /* process flow ctl err chars enable */
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unsigned lnext : 1; /* LNext option enable */
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unsigned istrip : 1; /* strip 8-bit on input */
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} cx_cor7_async_t;
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typedef struct { /* async channel options */
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cx_cor1_async_t cor1; /* channel option register 1 */
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cx_cor2_async_t cor2; /* channel option register 2 */
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cx_cor3_async_t cor3; /* option register 3 */
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cx_cor6_async_t cor6; /* channel option register 6 */
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cx_cor7_async_t cor7; /* channel option register 7 */
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unsigned char schr1; /* special character register 1 (XON) */
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unsigned char schr2; /* special character register 2 (XOFF) */
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unsigned char schr3; /* special character register 3 */
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unsigned char schr4; /* special character register 4 */
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unsigned char scrl; /* special character range low */
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unsigned char scrh; /* special character range high */
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unsigned char lnxt; /* LNext character */
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} cx_opt_async_t;
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/*
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* HDLC channel mode ---------------------------------------------------------
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*/
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/* Address field length option */
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#define AFLO_1OCT 0 /* address field is 1 octet in length */
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#define AFLO_2OCT 1 /* address field is 2 octet in length */
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/* Clear detect for X.21 data transfer phase */
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#define CLRDET_DISABLE 0 /* clear detect disabled */
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#define CLRDET_ENABLE 1 /* clear detect enabled */
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/* Addressing mode */
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#define ADMODE_NOADDR 0 /* no address */
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#define ADMODE_4_1 1 /* 4 * 1 byte */
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#define ADMODE_2_2 2 /* 2 * 2 byte */
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/* FCS append */
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#define FCS_NOTPASS 0 /* receive CRC is not passed to the host */
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#define FCS_PASS 1 /* receive CRC is passed to the host */
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/* CRC modes */
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#define CRC_INVERT 0 /* CRC is transmitted inverted (CRC V.41) */
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#define CRC_DONT_INVERT 1 /* CRC is not transmitted inverted (CRC-16) */
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/* Send sync pattern */
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#define SYNC_00 0 /* send 00h as pad char (NRZI encoding) */
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#define SYNC_AA 1 /* send AAh (Manchester/NRZ encoding) */
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/* FCS preset */
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#define FCSP_ONES 0 /* FCS is preset to all ones (CRC V.41) */
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#define FCSP_ZEROS 1 /* FCS is preset to all zeros (CRC-16) */
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/* idle mode */
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#define IDLE_FLAG 0 /* idle in flag */
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#define IDLE_MARK 1 /* idle in mark */
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/* CRC polynomial select */
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#define POLY_V41 0 /* x^16+x^12+x^5+1 (HDLC, preset to 1) */
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#define POLY_16 1 /* x^16+x^15+x^2+1 (bisync, preset to 0) */
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typedef struct { /* hdlc channel option register 1 */
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unsigned ifflags : 4; /* number of inter-frame flags sent */
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unsigned admode : 2; /* addressing mode */
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unsigned clrdet : 1; /* clear detect for X.21 data transfer phase */
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unsigned aflo : 1; /* address field length option */
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} cx_cor1_hdlc_t;
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typedef struct { /* hdlc channel option register 2 */
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unsigned dsrae : 1; /* DSR automatic enable */
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unsigned ctsae : 1; /* CTS automatic enable */
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unsigned rtsao : 1; /* RTS automatic output enable */
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unsigned zero1 : 1;
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unsigned crcninv : 1; /* CRC invertion option */
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unsigned zero2 : 1;
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unsigned fcsapd : 1; /* FCS append */
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unsigned zero3 : 1;
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} cx_cor2_hdlc_t;
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typedef struct { /* hdlc channel option register 3 */
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unsigned padcnt : 3; /* pad character count */
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unsigned idle : 1; /* idle mode */
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unsigned nofcs : 1; /* FCS disable */
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unsigned fcspre : 1; /* FCS preset */
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unsigned syncpat : 1; /* send sync pattern */
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unsigned sndpad : 1; /* send pad characters before flag enable */
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} cx_cor3_hdlc_t;
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typedef struct { /* hdlc channel options */
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cx_cor1_hdlc_t cor1; /* hdlc channel option register 1 */
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cx_cor2_hdlc_t cor2; /* hdlc channel option register 2 */
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cx_cor3_hdlc_t cor3; /* hdlc channel option register 3 */
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unsigned char rfar1; /* receive frame address register 1 */
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unsigned char rfar2; /* receive frame address register 2 */
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unsigned char rfar3; /* receive frame address register 3 */
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unsigned char rfar4; /* receive frame address register 4 */
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unsigned char cpsr; /* CRC polynomial select */
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} cx_opt_hdlc_t;
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/*
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* CD2400 channel state structure --------------------------------------------
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*/
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/* Signal encoding */
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#define ENCOD_NRZ 0 /* NRZ mode */
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#define ENCOD_NRZI 1 /* NRZI mode */
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#define ENCOD_MANCHESTER 2 /* Manchester mode */
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/* Clock source */
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#define CLK_0 0 /* clock 0 */
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#define CLK_1 1 /* clock 1 */
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#define CLK_2 2 /* clock 2 */
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#define CLK_3 3 /* clock 3 */
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#define CLK_4 4 /* clock 4 */
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#define CLK_EXT 6 /* external clock */
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#define CLK_RCV 7 /* receive clock */
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/* Board type */
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#define B_SIGMA_XXX 0 /* old Sigmas */
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#define B_SIGMA_2X 1 /* Sigma-22 */
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#define B_SIGMA_800 2 /* Sigma-800 */
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/* Channel type */
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#define T_NONE 0 /* no channel */
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#define T_ASYNC 1 /* pure asynchronous RS-232 channel */
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#define T_SYNC_RS232 2 /* pure synchronous RS-232 channel */
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#define T_SYNC_V35 3 /* pure synchronous V.35 channel */
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#define T_SYNC_RS449 4 /* pure synchronous RS-449 channel */
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#define T_UNIV_RS232 5 /* sync/async RS-232 channel */
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#define T_UNIV_RS449 6 /* sync/async RS-232/RS-449 channel */
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#define T_UNIV_V35 7 /* sync/async RS-232/V.35 channel */
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#define T_UNIV 8 /* sync/async, unknown interface */
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#define M_ASYNC 0 /* asynchronous mode */
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#define M_HDLC 1 /* bit-sync mode (HDLC) */
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typedef struct { /* channel option register 4 */
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unsigned thr : 4; /* FIFO threshold */
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unsigned zero : 1;
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unsigned cts_zd : 1; /* detect 1 to 0 transition on the CTS */
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unsigned cd_zd : 1; /* detect 1 to 0 transition on the CD */
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unsigned dsr_zd : 1; /* detect 1 to 0 transition on the DSR */
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} cx_cor4_t;
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typedef struct { /* channel option register 5 */
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unsigned rx_thr : 4; /* receive flow control FIFO threshold */
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unsigned zero : 1;
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unsigned cts_od : 1; /* detect 0 to 1 transition on the CTS */
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unsigned cd_od : 1; /* detect 0 to 1 transition on the CD */
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unsigned dsr_od : 1; /* detect 0 to 1 transition on the DSR */
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} cx_cor5_t;
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typedef struct { /* receive clock option register */
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unsigned clk : 3; /* receive clock source */
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unsigned encod : 2; /* signal encoding NRZ/NRZI/Manchester */
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unsigned dpll : 1; /* DPLL enable */
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unsigned zero : 1;
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unsigned tlval : 1; /* transmit line value */
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} cx_rcor_t;
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typedef struct { /* transmit clock option register */
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unsigned zero1 : 1;
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unsigned llm : 1; /* local loopback mode */
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unsigned zero2 : 1;
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unsigned ext1x : 1; /* external 1x clock mode */
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unsigned zero3 : 1;
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unsigned clk : 3; /* transmit clock source */
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} cx_tcor_t;
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typedef struct {
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cx_cor4_t cor4; /* channel option register 4 */
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cx_cor5_t cor5; /* channel option register 5 */
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cx_rcor_t rcor; /* receive clock option register */
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cx_tcor_t tcor; /* transmit clock option register */
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} cx_chan_opt_t;
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typedef enum { /* line break mode */
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BRK_IDLE, /* normal line mode */
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BRK_SEND, /* start sending break */
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BRK_STOP, /* stop sending break */
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} cx_break_t;
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#define BUS_NORMAL 0 /* normal bus timing */
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#define BUS_FAST 1 /* fast bus timing (Sigma-22 and -800) */
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#define BUS_FAST2 2 /* fast bus timing (Sigma-800) */
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#define BUS_FAST3 3 /* fast bus timing (Sigma-800) */
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typedef struct { /* board options */
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unsigned char fast; /* bus master timing (Sigma-22 and -800) */
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} cx_board_opt_t;
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#define NCHIP 4 /* the number of controllers per board */
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#define NCHAN 16 /* the number of channels on the board */
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typedef struct {
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unsigned char tbuffer [2] [DMABUFSZ];
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unsigned char rbuffer [2] [DMABUFSZ];
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} cx_buf_t;
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typedef struct _cx_chan_t {
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struct _cx_board_t *board; /* board pointer */
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unsigned char type; /* channel type */
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unsigned char num; /* channel number, 0..15 */
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port_t port; /* base port address */
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unsigned long oscfreq; /* oscillator frequency in Hz */
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unsigned long rxbaud; /* receiver speed */
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unsigned long txbaud; /* transmitter speed */
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unsigned char mode; /* channel mode */
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cx_chan_opt_t opt; /* common channel options */
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cx_opt_async_t aopt; /* async mode options */
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cx_opt_hdlc_t hopt; /* hdlc mode options */
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unsigned char *arbuf; /* receiver A dma buffer */
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unsigned char *brbuf; /* receiver B dma buffer */
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unsigned char *atbuf; /* transmitter A dma buffer */
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unsigned char *btbuf; /* transmitter B dma buffer */
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unsigned long arphys; /* receiver A phys address */
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unsigned long brphys; /* receiver B phys address */
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unsigned long atphys; /* transmitter A phys address */
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unsigned long btphys; /* transmitter B phys address */
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unsigned char dtr; /* DTR signal value */
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unsigned char rts; /* RTS signal value */
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unsigned long rintr; /* receive interrupts */
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unsigned long tintr; /* transmit interrupts */
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unsigned long mintr; /* modem interrupts */
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unsigned long ibytes; /* input bytes */
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unsigned long ipkts; /* input packets */
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unsigned long ierrs; /* input errors */
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unsigned long obytes; /* output bytes */
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unsigned long opkts; /* output packets */
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unsigned long oerrs; /* output errors */
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void *sys;
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int debug;
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void *attach [2];
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char *received_data;
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int received_len;
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int overflow;
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void (*call_on_rx) (struct _cx_chan_t*, char*, int);
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void (*call_on_tx) (struct _cx_chan_t*, void*, int);
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void (*call_on_msig) (struct _cx_chan_t*);
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void (*call_on_err) (struct _cx_chan_t*, int);
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} cx_chan_t;
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typedef struct _cx_board_t {
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unsigned char type; /* board type */
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unsigned char num; /* board number, 0..2 */
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port_t port; /* base board port, 0..3f0 */
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unsigned char irq; /* irq {3 5 7 10 11 12 15} */
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unsigned char dma; /* DMA request {5 6 7} */
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char name[16]; /* board version name */
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unsigned char nuniv; /* number of universal channels */
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unsigned char nsync; /* number of sync. channels */
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unsigned char nasync; /* number of async. channels */
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unsigned char if0type; /* chan0 interface RS-232/RS-449/V.35 */
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unsigned char if8type; /* chan8 interface RS-232/RS-449/V.35 */
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unsigned short bcr0; /* BCR0 image */
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unsigned short bcr0b; /* BCR0b image */
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unsigned short bcr1; /* BCR1 image */
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unsigned short bcr1b; /* BCR1b image */
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cx_board_opt_t opt; /* board options */
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cx_chan_t chan[NCHAN]; /* channel structures */
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void *sys;
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} cx_board_t;
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extern long cx_rxbaud, cx_txbaud;
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extern int cx_univ_mode, cx_sync_mode, cx_iftype;
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extern cx_chan_opt_t chan_opt_dflt; /* default mode-independent options */
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extern cx_opt_async_t opt_async_dflt; /* default async options */
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extern cx_opt_hdlc_t opt_hdlc_dflt; /* default hdlc options */
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extern cx_board_opt_t board_opt_dflt; /* default board options */
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struct _cr_dat_tst;
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int cx_probe_board (port_t port, int irq, int dma);
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void cx_init (cx_board_t *b, int num, port_t port, int irq, int dma);
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void cx_init_board (cx_board_t *b, int num, port_t port, int irq, int dma,
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int chain, int rev, int osc, int mod, int rev2, int osc2, int mod2);
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void cx_init_2x (cx_board_t *b, int num, port_t port, int irq, int dma,
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int rev, int osc);
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void cx_init_800 (cx_board_t *b, int num, port_t port, int irq, int dma,
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int chain);
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int cx_download (port_t port, const unsigned char *firmware, long bits,
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const struct _cr_dat_tst *tst);
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int cx_setup_board (cx_board_t *b, const unsigned char *firmware,
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long bits, const struct _cr_dat_tst *tst);
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void cx_setup_chan (cx_chan_t *c);
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void cx_update_chan (cx_chan_t *c);
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void cx_set_dtr (cx_chan_t *c, int on);
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void cx_set_rts (cx_chan_t *c, int on);
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void cx_led (cx_board_t *b, int on);
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void cx_cmd (port_t base, int cmd);
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void cx_disable_dma (cx_board_t *b);
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void cx_reinit_board (cx_board_t *b);
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int cx_get_dsr (cx_chan_t *c);
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int cx_get_cts (cx_chan_t *c);
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int cx_get_cd (cx_chan_t *c);
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void cx_clock (long hz, long ba, int *clk, int *div);
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/* DDK errors */
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#define CX_FRAME 1
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#define CX_CRC 2
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#define CX_OVERRUN 3
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#define CX_OVERFLOW 4
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#define CX_UNDERRUN 5
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#define CX_BREAK 6
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/* clock sources */
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#define CX_CLK_INT 0
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#define CX_CLK_EXT 6
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#define CX_CLK_RCV 7
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#define CX_CLK_DPLL 8
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#define CX_CLK_DPLL_EXT 14
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/* functions dealing with interrupt vector in DOS */
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#if defined (MSDOS) || defined (__MSDOS__)
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int ddk_int_alloc (int irq, void (*func)(), void *arg);
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int ddk_int_restore (int irq);
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#endif
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int cx_probe_irq (cx_board_t *b, int irq);
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void cx_int_handler (cx_board_t *b);
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int cx_find (port_t *board_ports);
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int cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma);
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void cx_close_board (cx_board_t *b);
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void cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys);
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/*
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Set port type for old models of Sigma
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*/
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void cx_set_port (cx_chan_t *c, int iftype);
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/*
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Get port type for old models of Sigma
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-1 Fixed port type or auto detect
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0 RS232
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1 V35
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2 RS449
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*/
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int cx_get_port (cx_chan_t *c);
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void cx_enable_receive (cx_chan_t *c, int on);
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void cx_enable_transmit (cx_chan_t *c, int on);
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int cx_receive_enabled (cx_chan_t *c);
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int cx_transmit_enabled (cx_chan_t *c);
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void cx_set_baud (cx_chan_t *, unsigned long baud);
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int cx_set_mode (cx_chan_t *c, int mode);
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void cx_set_loop (cx_chan_t *c, int on);
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void cx_set_nrzi (cx_chan_t *c, int nrzi);
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void cx_set_dpll (cx_chan_t *c, int on);
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unsigned long cx_get_baud (cx_chan_t *c);
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int cx_get_loop (cx_chan_t *c);
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int cx_get_nrzi (cx_chan_t *c);
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int cx_get_dpll (cx_chan_t *c);
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int cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment);
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int cx_buf_free (cx_chan_t *c);
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void cx_register_transmit (cx_chan_t *c,
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void (*func) (cx_chan_t *c, void *attachment, int len));
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void cx_register_receive (cx_chan_t *c,
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void (*func) (cx_chan_t *c, char *data, int len));
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void cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c));
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void cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data));
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void cx_intr_off (cx_board_t *b);
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void cx_intr_on (cx_board_t *b);
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int cx_checkintr (cx_board_t *b);
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/* Async functions */
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void cx_transmitter_ctl (cx_chan_t *c, int start);
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void cx_flush_transmit (cx_chan_t *c);
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void cx_xflow_ctl (cx_chan_t *c, int on);
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void cx_send_break (cx_chan_t *c, int msec);
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void cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity,
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int stop2, int ignpar, int rtscts,
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int ixon, int ixany, int symstart, int symstop);
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